Patent US3714519A successfully refreshed from Google Patents.
US3714519A
Expired / Lapsed
US
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Solid state timer
Assignee: Individual
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Filing: 1970-10-05
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Granted: 1973-01-30
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Expires: 1990-10-05
Abstract
Abstract A solid state timer powered by a direct current source and including means for generating pulses at timed intervals for delivery to a shift register including a series of flip-flop solid state units and operative after application thereto of a predetermined number of pulses to change its condition and thereby activate a controlled unit. Reset means respond to each activation of said shift register means to restore it to condition to repeat its operation.
Inventors
- 👤 J Swinea
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:14
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/28
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
181 words
A solid state timer comprising a closed trigger circuit including a uni-junction transistor and operable for generating pulses at timed intervals of duration of at least multiple seconds and having a supply line including a resistor and a charging capacitor, a shift register circuit including a plurality of series-connected solid state flip-flop units, said shift register circuit being responsive to said trigger circuit pulses and operable to produce an output signal after a selected number of pulses and a duration of multiple minutes or hours, intermittently operable control means responsive to each output signal, and means for resetting said shift register circuit after delivery of each output signal and including means for changing the time of timed intervals by means providing a new and additional charging path for said clocked trigger circuit and including a second supply line having a resistor connected in parallel to said first supply line, a diode preventing draining of the charging capacitor for said transistor, and switch means responsive to said output signal for activating said additional charging path to said uni-junction transistor through said diode.
Claim 2
Dependent Claim
181 words
A solid state timer comprising a closed trigger circuit including a uni-junction transistor and operable for generating pulses at timed intervals of duration of at least multiple seconds and having a supply line including a resistor and a charging capacitor, a shift register circuit including a plurality of series-connected solid state flip-flop units, said shift register circuit being responsive to said trigger circuit pulses and operable to produce an output signal after a selected number of pulses and a duration of multiple minutes or hours, intermittently operable control means responsive to each output signal, and means for resetting said shift register circuit after delivery of each output signal and including means for changing the time of timed intervals by means providing a new and additional charging path for said clocked trigger circuit and including a second supply line having a resistor connected in parallel to said first supply line, a diode preventing draining of the charging capacitor for said transistor, and switch means responsive to said output signal for activating said additional charging path to said uni-junction transistor through said diode.
Claim 3
Dependent Claim
181 words
A solid state timer comprising a closed trigger circuit including a uni-junction transistor and operable for generating pulses at timed intervals of duration of at least multiple seconds and having a supply line including a resistor and a charging capacitor, a shift register circuit including a plurality of series-connected solid state flip-flop units, said shift register circuit being responsive to said trigger circuit pulses and operable to produce an output signal after a selected number of pulses and a duration of multiple minutes or hours, intermittently operable control means responsive to each output signal, and means for resetting said shift register circuit after delivery of each output signal and including means for changing the time of timed intervals by means providing a new and additional charging path for said clocked trigger circuit and including a second supply line having a resistor connected in parallel to said first supply line, a diode preventing draining of the charging capacitor for said transistor, and switch means responsive to said output signal for activating said additional charging path to said uni-junction transistor through said diode.
Claim 4
Dependent Claim
181 words
A solid state timer comprising a closed trigger circuit including a uni-junction transistor and operable for generating pulses at timed intervals of duration of at least multiple seconds and having a supply line including a resistor and a charging capacitor, a shift register circuit including a plurality of series-connected solid state flip-flop units, said shift register circuit being responsive to said trigger circuit pulses and operable to produce an output signal after a selected number of pulses and a duration of multiple minutes or hours, intermittently operable control means responsive to each output signal, and means for resetting said shift register circuit after delivery of each output signal and including means for changing the time of timed intervals by means providing a new and additional charging path for said clocked trigger circuit and including a second supply line having a resistor connected in parallel to said first supply line, a diode preventing draining of the charging capacitor for said transistor, and switch means responsive to said output signal for activating said additional charging path to said uni-junction transistor through said diode.
Claim 5
Dependent Claim
25 words
A solid state timer as defined in claim 1, including a direct current power source and a line voltage regulator feeding said clocked trigger circuit.
Claim 6
Dependent Claim
38 words
A solid state timer as defined in claim 1, wherein said clocked trigger circuit produces pulses at a selected rate when energized by said first supply line and at a different rate when energized by both supply lines.
Claim 7
Dependent Claim
54 words
A solid state timer as defined in claim 3, wherein said clocked trigger circuit includes a normally inoperative branch circuit in parallel thereto and having a normally open switch and resistance means different from said first named resistance means and cooperating with said capacitor and transistor to produce said pulses at a third rate.
Claim 8
Dependent Claim
47 words
A solid state timer as defined in claim 1, wherein said clocked trigger circuit and resetting means includes a unijunction transistor and alternately operable means including said first and second supply lines for delivering a charge to said transistor at selected alternate and different intervals of time.
Claim 9
Dependent Claim
39 words
A solid state timer as defined in claim 1, wherein said clocked trigger circuit includes a uni-junction transistor, and an inverter interposed between said transistor and said shift register circuit to shape pulses delivered to said shift register circuit.
Claim 10
Dependent Claim
19 words
A solid state timer as defined in claim 1, wherein said control means includes a transistor and a load.
Claim 11
Dependent Claim
34 words
A solid state timer as defined in claim 1, wherein said control means includes a group of transistors connected to a load to activate a current path from a power source to said load.
Claim 12
Dependent Claim
42 words
A solid state timer as defined in claim 3, wherein said reset means includes a lead connecting the output of the shift register with said second supply line to said clocked trigger circuit and having a transistor controllIng said second supply line.
Claim 13
Dependent Claim
58 words
A solid state timer as defined in claim 1, wherein said shift register circuit normally delivers a charge to a transistor forming part of said control means, said shift register circuit responding only to negative transitions and reducing the voltage applied to the transistor of said control means when said selected number of pulses have been applied thereto.
Claim 14
Dependent Claim
33 words
A solid state timer as defined in claim 1, and a buffer means interposed between the output of said shift register circuit and a load member of the type including relays and solenoids.
Claim 15
Dependent Claim
47 words
A solid state timer as defined in claim 1, wherein an inverter means connected to be energized by the output of said shift register circuit upon passage of said selected number of pulses through said shift register circuit is connected to a terminal of each flip-flop unit.
Claim 16
Dependent Claim
36 words
A solid state timer as defined in claim 12, and means connected to said inverter means and including a diode, a capacitor and a resistor functioning to prevent a race condition when power is applied thereto.
Claim 17
Dependent Claim
99 words
A solid state timer as defined in claim 12, wherein a plurality of inverters are connected to be energized by the output of said shift register circuit, one of said inverters having a terminal connected to a terminal of the initial flip-flop unit of said shift register circuit, another inverter being connected to the reset terminals of said flip-flop units of said shift register circuit to supply a resetting impulse, and means for imparting a positive impulse to said last named inverter while the state of the first inverter is low, for the purpose of resetting said flip-flop units.
Claim 18
Dependent Claim
34 words
A solid state timer as defined in claim 1, wherein said flip-flop units are so connected that the time lapses between energization of successive flip-flop units of said shift register increases in geometric progression.
Claim 19
Dependent Claim
21 words
A solid state timer as defined in claim 1, wherein said trigger circuit, shift register circuit and resetting means are encapsulated.
Claim 20
Dependent Claim
23 words
A solid state timer as defined in claim 12 and second means cooperating with said clocked trigger circuit for resetting said shift register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-30 | 1976-07-31 | 1977-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-30 | 1980-07-31 | 1981-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-30 | 1984-07-31 | 1985-01-30 | $7700.00 | Window Closed / Lapsed |