Digital frequency and/or phase detector charge pump

Claim 2

A digital control circuit for comparing relative time positions of corresponding portions of first and second external time varying signals comprising: a first J-K flip flop having two stable states and having a first two logic level input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said first two logic level input means energized at one logic level, and the other of said first two logic level input means energized at a second logic level; the signal input means of said first J-K flip flops connected to directly receive, of said first and second external time varying signals, only said first external time varying signal; said first J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of said corresponding portion of said first external time varying signal, a first output signal on the output signal means of said first J-K flip flop; a second J-K flip flop having two stable states and having a second two logic levels input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said second two logic input means energized at one logic level, and the other of said two logic means energized at a second logic level; the signal input means of said second J-K flip flop connected to directly receive, of said first and second external time varying signals, only said second external time varying signal; said second J-K flip flop being adapted in one of its states to provide, in response to the occurrence of said corresponding portion of said second external time varying signal, a second output signal on the output signal means of said second J-K flip flop; said one of said first two logic level input means and said one of said second two logic level means connected together; said other one of said first two logic level input means, the reset input means of said first J-K flip flop, said other one of said second two logic level input means, and the set input means of said second J-K flip flop connected together; logic means for comparing said first and second output signals and providing a change of state output signal upon the occurrence of the second one of said corresponding portions of said first and second external time varying signals; and means for applying said change of state signal to the set input means of said first J-K flip flop and to the reset input means of said second J-K flip flop.

Claim 3

A digital control circuit for comparing relative time positions of corresponding portions of first and second external time varying signals comprising: a first J-K flip flop having two stable states and having a first two logic level input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said first two logic level input means energized at one logic level, and the other of said first two logic level input means energized at a second logic level; the signal input means of said first J-K flip flops connected to directly receive, of said first and second external time varying signals, only said first external time varying signal; said first J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of said corresponding portion of said first external time varying signal, a first output signal on the output signal means of said first J-K flip flop; a second J-K flip flop having two stable states and having a second two logic levels input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said second two logic input means energized at one logic level, and the other of said two logic means energized at a second logic level; the signal input means of said second J-K flip flop connected to directly receive, of said first and second external time varying signals, only said second external time varying signal; said second J-K flip flop being adapted in one of its states to provide, in response to the occurrence of said corresponding portion of said second external time varying signal, a second output signal on the output signal means of said second J-K flip flop; said one of said first two logic level input means and said one of said second two logic level means connected together; said other one of said first two logic level input means, the reset input means of said first J-K flip flop, said other one of said second two logic level input means, and the set input means of said second J-K flip flop connected together; logic means for comparing said first and second output signals and providing a change of state output signal upon the occurrence of the second one of said corresponding portions of said first and second external time varying signals; and means for applying said change of state signal to the set input means of said first J-K flip flop and to the reset input means of said second J-K flip flop.

Claim 4

A digital control circuit for comparing relative time positions of corresponding portions of first and second external time varying signals comprising: a first J-K flip flop having two stable states and having a first two logic level input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said first two logic level input means energized at one logic level, and the other of said first two logic level input means energized at a second logic level; the signal input means of said first J-K flip flops connected to directly receive, of said first and second external time varying signals, only said first external time varying signal; said first J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of said corresponding portion of said first external time varying signal, a first output signal on the output signal means of said first J-K flip flop; a second J-K flip flop having two stable states and having a second two logic levels input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said second two logic input means energized at one logic level, and the other of said two logic means energized at a second logic level; the signal input means of said second J-K flip flop connected to directly receive, of said first and second external time varying signals, only said second external time varying signal; said second J-K flip flop being adapted in one of its states to provide, in response to the occurrence of said corresponding portion of said second external time varying signal, a second output signal on the output signal means of said second J-K flip flop; said one of said first two logic level input means and said one of said second two logic level means connected together; said other one of said first two logic level input means, the reset input means of said first J-K flip flop, said other one of said second two logic level input means, and the set input means of said second J-K flip flop connected together; logic means for comparing said first and second output signals and providing a change of state output signal upon the occurrence of the second one of said corresponding portions of said first and second external time varying signals; and means for applying said change of state signal to the set input means of said first J-K flip flop and to the reset input means of said second J-K flip flop.

Claim 5

A digital control circuit for comparing relative time positions of corresponding portions of first and second external time varying signals comprising: a first J-K flip flop having two stable states and having a first two logic level input means, a set input means, a reset input means, a signal input means, an output signal means, and a complementary output signal means, one of said first two logic level input means energized at one logic level, and the other of said first two logic level input means energized at a second logic level; the signal input means of said first J-K flip flops connected to directly receive, of said first and second external time varying signals, only said first external time varying signal; said first J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of said corresponding portion of said first external time varying signal, a first output signal on the output signal means of said first J-K flip flop and the complement of said first output signal on the complementary output signal means of said first J-K flip flop; a second J-K flip flop having two stable states and having a second two logic levels input means, a set input means, a reset input means, a signal input means, an output signal means, and a complementary output signal means, one of said second two logic input means energized at one logic level, and the other of said two logic means energized at a second logic level; the signal input means of said second J-K flip flop connected to directly receive, of said first and second external time varying signals, only said second external time varying signal; said second J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of said corresponding portion of said second external time varying signal, a second output signal on the output signal means of said second J-K flip flop and the complement of said second output signal on the complementary output signal means of said second J-K flip flop; said one of said first two logic level input means and said one of said second two logic level means connected together; said other one of said first two logic level input means, the reset input means of said first J-K flip flop, said other one of said second two logic level input means, and the set input means of said second J-K flip flop connected together; logic means for comparing one of said first output signal and the complement of said first output signal with one of said complements of said second output signal and said second output signal, respectively, and providing a change of state output signal upon the occurrence of the second one of said corresponding portions of said first and second external time varying siGnals; and means for applying said change of state signal to the set input means of said first J-K flip flop and to the reset input means of said second J-K flip flop.

Claim 6

A digital control circuit for comparing relative time positions of corresponding portions of first and second external time varying signals comprising: a first J-K flip flop having two stable states and having a first two logic level input means, a set input means, a reset input means, a signal input means, an output signal means, and a complementary output signal means, one of said first two logic level input means energized at one logic level, and the other of said first two logic level input means energized at a second logic level; the signal input means of said first J-K flip flops connected to directly receive, of said first and second external time varying signals, only said first external time varying signal; said first J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of said corresponding portion of said first external time varying signal, a first output signal on the output signal means of said first J-K flip flop and the complement of said first output signal on the complementary output signal means of said first J-K flip flop; a second J-K flip flop having two stable states and having a second two logic levels input means, a set input means, a reset input means, a signal input means, an output signal means, and a complementary output signal means, one of said second two logic input means energized at one logic level, and the other of said two logic means energized at a second logic level; the signal input means of said second J-K flip flop connected to directly receive, of said first and second external time varying signals, only said second external time varying signal; said second J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of said corresponding portion of said second external time varying signal, a second output signal on the output signal means of said second J-K flip flop and the complement of said second output signal on the complementary output signal means of said second J-K flip flop; said one of said first two logic level input means and said one of said second two logic level means connected together; said other one of said first two logic level input means, the reset input means of said first J-K flip flop, said other one of said second two logic level input means, and the set input means of said second J-K flip flop connected together; logic means for comparing one of said first output signal and the complement of said first output signal with one of said complements of said second output signal and said second output signal, respectively, and providing a change of state output signal upon the occurrence of the second one of said corresponding portions of said first and second external time varying siGnals; and means for applying said change of state signal to the set input means of said first J-K flip flop and to the reset input means of said second J-K flip flop.

Claim 7

A digital control circuit for comparing relative time positions of corresponding portions of first and second external time varying signals comprising: a first J-K flip flop having two stable states and having a first two logic level input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said first two logic level input means energized at one logic level, and the other of said first two logic level input means energized at a second logic level; the signal input means of said first J-K flip flop connected to directly receive, of said first and second external time varying signals, only said first external time varying signal; said first J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of said corresponding portion of said first external time varying signal, a first output signal on the output signal means of said first J-K flip flop; a second J-K flip flop having two stable states and having a second two logic levels input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said second two logic input means energized at one logic level, and the other of said two logic means energized at a second logic level; the signal input means of said second J-K flip flop connected to directly receive, of said first and second time varying signals, only said second external time varying signal; said second J-K flip flop being adapted in one of its stable states to provide in response to the occurrence of said corresponding portion of said second external time varying signal, a second output signal on the output signal means of said second J-K flip flop; said one of said first two logic level input means and said one of said second two logic level means connected together; said other one of said first two logic level input means, the reset input means of said first J-K flip flop, said other one of said second two logic level input means, and the set input means of said second J-K flip flop connected together; logic means for comparing said first and second output signals and providing a change of state output signal upon the occurrence of the second one of said corresponding portions of said first and second external time varying signals; further logic means responsive to said first and said second output signals for controlling an analog voltage in accordance with the time interval between said corresponding portions of said first and second external time varying signals; and means for applying said change of state signal to the set input means of said first J-K flip flop and to the reset input means of said second J-K flip flop.

Claim 8

A digital control circuit for comparing relative time positions of corresponding portions of first and second external time varying signals comprising: a first J-K flip flop having two stable states and having a first two logic level input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said first two logic level input means energized at one logic level, and the other of said first two logic level input means energized at a second logic level; the signal input means of said first J-K flip flop connected to directly receive, of said first and second external time varying signals, only said first external time varying signal; said first J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of said corresponding portion of said first external time varying signal, a first output signal on the output signal means of said first J-K flip flop; a second J-K flip flop having two stable states and having a second two logic levels input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said second two logic input means energized at one logic level, and the other of said two logic means energized at a second logic level; the signal input means of said second J-K flip flop connected to directly receive, of said first and second time varying signals, only said second external time varying signal; said second J-K flip flop being adapted in one of its stable states to provide in response to the occurrence of said corresponding portion of said second external time varying signal, a second output signal on the output signal means of said second J-K flip flop; said one of said first two logic level input means and said one of said second two logic level means connected together; said other one of said first two logic level input means, the reset input means of said first J-K flip flop, said other one of said second two logic level input means, and the set input means of said second J-K flip flop connected together; logic means for comparing said first and second output signals and providing a change of state output signal upon the occurrence of the second one of said corresponding portions of said first and second external time varying signals; further logic means responsive to said first and said second output signals for controlling an analog voltage in accordance with the time interval between said corresponding portions of said first and second external time varying signals; and means for applying said change of state signal to the set input means of said first J-K flip flop and to the reset input means of said second J-K flip flop.

Claim 9

A digital control circuit for comparing relative time positions of corresponding portions of first and second external time varying signals comprising: a first J-K flip flop having two stable states and having a first two logic level input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said first two logic level input means energized at one logic level, and the other of said first two logic level input means energized at a second logic level; the signal input means of said first J-K flip flops connected to directly receive, of said first and second external time varying signals, only said first external time varying signal; said first J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of said corresponding portion of said first external time varying signal, a first output signal on the output signal means of said first J-K flip flop; a second J-K flip flop having two stable states and having a second two logiC levels input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said second two logic input means energized at one logic level, and the other of said two logic means energized at a second logic level; the signal input means of said second J-K flip flop connected to directly receive, of said first and second external time varying signals, only said second external time varying signal; said second J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of said corresponding portion of said second external time varying signal, a second output signal on the output signal means of said second J-K flip flop; said one of said first two logic level input means and said one of said second two logic level means connected together; said other one of said first two logic level input means, the reset input means of said first J-K flip flop, said other one of said second two logic level input means, and the set input means of said second J-K flip flop connected together; logic means for comparing said first and second output signals and providing a change of state output signal upon the occurrence of the second one of said corresponding portions of said first and second external time varying signals, further logic means responsive to said first and said second output signals for controlling an energizing circuit to supply an analog voltage member in accordance with the time interval between said corresponding portions of said first and said second external time varying signals; and means for applying said change of state signal to the set input means of said first J-K flip flop and to the reset input means of said second J-K flip flop.

Claim 10

A digital control circuit for comparing relative time positions of corresponding portions of first and second external time varying signals comprising: a first J-K flip flop having two stable states and having a first two logic level input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said first two logic level input means energized at one logic level, and the other of said first two logic level input means energized at a second logic level; the signal input means of said first J-K flip flops connected to directly receive, of said first and second external time varying signals, only said first external time varying signal; said first J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of said corresponding portion of said first external time varying signal, a first output signal on the output signal means of said first J-K flip flop; a second J-K flip flop having two stable states and having a second two logiC levels input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said second two logic input means energized at one logic level, and the other of said two logic means energized at a second logic level; the signal input means of said second J-K flip flop connected to directly receive, of said first and second external time varying signals, only said second external time varying signal; said second J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of said corresponding portion of said second external time varying signal, a second output signal on the output signal means of said second J-K flip flop; said one of said first two logic level input means and said one of said second two logic level means connected together; said other one of said first two logic level input means, the reset input means of said first J-K flip flop, said other one of said second two logic level input means, and the set input means of said second J-K flip flop connected together; logic means for comparing said first and second output signals and providing a change of state output signal upon the occurrence of the second one of said corresponding portions of said first and second external time varying signals, further logic means responsive to said first and said second output signals for controlling an energizing circuit to supply an analog voltage member in accordance with the time interval between said corresponding portions of said first and said second external time varying signals; and means for applying said change of state signal to the set input means of said first J-K flip flop and to the reset input means of said second J-K flip flop.

Claim 11

A digital control circuit according to claim 4 wherein said further logic means comprises one logic device responsive to said first output signal and a second logic device responsive to said second output signal; said energizing circuit comprises a series circuit for first transistor responsive to an output signal from said one logic device, a second transistor responsive to an output signal from said second logic device and a voltage source thereacross; and said analog voltage member comprises a capacitor and resistor connected between one terminal of said voltage source and the juncture of said first and second transistors.

Claim 12

A digital control circuit for detecting the relative phase between an external time varying signal and an external time varying signal responsive to such phase which is fed back from the output of such circuit comprising: a first J-K flip flop having two stable states and having a first two logic level input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said first two logic level input means energized at one logic level, and the other of said first two logic level input means energized at a second logic level; the signal input means of said first J-K flip flops connected to directly receive, of said external reference signal and said external feedback signal, only said external reference signal; said first J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of a specified condition of said first external reference signal, a first output signal on the output signal means of said first J-K flip flop; a second J-K flip flop having two stable states and having a second two logic levels input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said second two logic input means energized at one logic level, and the other of said two logic means energized at a second logic level; the signal input means of said second J-K flip flop connected to directly receive of said external reference signal and said external feedback signal only said external time varying fed back signal; said second J-K flip Flop being adapted in one of its stable states to provide, in response to the occurrence of the same specified condition of said external time varying fed back signal, a second output signal on the output signal means of said second J-K flip flop; said one of said first two logic level input means and said one of said second two logic level means connected together; said other one of said first two logic level input means, the reset input means of said first J-K flip flop, said other one of said second two logic level input means, and the set input means of said second J-K flip flop connected together; logic means for comparing said first and second output signals and providing a change of state output signal upon the occurrence of the second one of said specified conditions of said external time varying reference and fed back signals; means for applying said change of state signal to the set input means of said first J-K flip flop and to the reset input means of said second J-K flip flop; and means for generating an output signal in accordance with the phase difference between said specified condition of said external reference and fed back time varying signals.

Claim 13

A digital control circuit for detecting the relative phase between an external time varying signal and an external time varying signal responsive to such phase which is fed back from the output of such circuit comprising: a first J-K flip flop having two stable states and having a first two logic level input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said first two logic level input means energized at one logic level, and the other of said first two logic level input means energized at a second logic level; the signal input means of said first J-K flip flops connected to directly receive, of said external reference signal and said external feedback signal, only said external reference signal; said first J-K flip flop being adapted in one of its stable states to provide, in response to the occurrence of a specified condition of said first external reference signal, a first output signal on the output signal means of said first J-K flip flop; a second J-K flip flop having two stable states and having a second two logic levels input means, a set input means, a reset input means, a signal input means, and an output signal means, one of said second two logic input means energized at one logic level, and the other of said two logic means energized at a second logic level; the signal input means of said second J-K flip flop connected to directly receive of said external reference signal and said external feedback signal only said external time varying fed back signal; said second J-K flip Flop being adapted in one of its stable states to provide, in response to the occurrence of the same specified condition of said external time varying fed back signal, a second output signal on the output signal means of said second J-K flip flop; said one of said first two logic level input means and said one of said second two logic level means connected together; said other one of said first two logic level input means, the reset input means of said first J-K flip flop, said other one of said second two logic level input means, and the set input means of said second J-K flip flop connected together; logic means for comparing said first and second output signals and providing a change of state output signal upon the occurrence of the second one of said specified conditions of said external time varying reference and fed back signals; means for applying said change of state signal to the set input means of said first J-K flip flop and to the reset input means of said second J-K flip flop; and means for generating an output signal in accordance with the phase difference between said specified condition of said external reference and fed back time varying signals.

Claim 14

The digital control circuit according to claim 6 wherein said means for generating an output signal comprises further logic means responsive to said first and second output signals for controlling an output circuit in accordance with the phase difference between said specific conditions of said external reference and fed back time varying signals.

Claim 15

A digital control circuit according to claim 7 wherein said further logic means comprises one logic device responsive to said first output signal and a second logic device responsive to said second output signal; said output circuit comprises a series circuit for first transistor responsive to an output signal from said one logic device, a second transistor responsive to an output signal from said second logic device, a voltage source thereacross, and a voltage responsive member connected between one terminal of said voltage source and the juncture of said first and second transistors.

Claim 16

A digital control circuit for detecting the phase between an external time varying reference signal and an external time varying signal responsive to such phase which is fed back from the output of such circuit comprising a first bistable means adapted to receive of said external references signal and said external feedback signal only said external reference signal, and being adapted in one of its bistable states to provide, in response to the occurrence of a specified condition of said external reference signal, an output signal; a second bistable means adapted to receive only said external time varying fed back signal, and being adapted in one of its bistable states to provide, in response to the occurrence of the same specified condition of said external time varying fed back signal, a second output signal; logic means for comparing said first and second output signals and providing a change of state output signal upon the occurrence of the second one of said specified conditions of said external time varying reference and fed back signals; means for applying said change of state signal to said first and second bistable means; further logic means responsive to said first and second output signals for controlling an output circuit in accordance with the phase difference between said specific conditions of said external reference and fed back time varying signals; said further logic means comprises one logic device responsive to said first output signal and a second logic device responsive to said second output signal; said output circuit comprises a series circuit for first transistor responsive to an output signal from said one logic device, a second transistor responsive to an output signal from said second logic device, a voltage source thereacross, and a voltage responsive member connected bEtween one terminal of said voltage source and the juncture of said first and second transistors; and a voltage controlled oscillator energized by the voltage of said voltage responsive member, the output time varying signal of said oscillator being fed back to said second bistable means.

Claim 17

A digital control circuit for detecting the phase between an external time varying reference signal and an external time varying signal responsive to such phase which is fed back from the output of such circuit comprising a first bistable means adapted to receive of said external references signal and said external feedback signal only said external reference signal, and being adapted in one of its bistable states to provide, in response to the occurrence of a specified condition of said external reference signal, an output signal; a second bistable means adapted to receive only said external time varying fed back signal, and being adapted in one of its bistable states to provide, in response to the occurrence of the same specified condition of said external time varying fed back signal, a second output signal; logic means for comparing said first and second output signals and providing a change of state output signal upon the occurrence of the second one of said specified conditions of said external time varying reference and fed back signals; means for applying said change of state signal to said first and second bistable means; further logic means responsive to said first and second output signals for controlling an output circuit in accordance with the phase difference between said specific conditions of said external reference and fed back time varying signals; said further logic means comprises one logic device responsive to said first output signal and a second logic device responsive to said second output signal; said output circuit comprises a series circuit for first transistor responsive to an output signal from said one logic device, a second transistor responsive to an output signal from said second logic device, a voltage source thereacross, and a voltage responsive member connected bEtween one terminal of said voltage source and the juncture of said first and second transistors; and a voltage controlled oscillator energized by the voltage of said voltage responsive member, the output time varying signal of said oscillator being fed back to said second bistable means.

Claim 18

The digital control circuit according to claim 9 wherein the voltage controlled oscillator includes means for varying its frequency.