US3714461A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Generation of multilevel digital waveforms
Assignee: Nortel Networks Technology Corp
•
Filing: 1971-11-05
•
Granted: 1973-01-30
•
Expires: 1991-11-05
Abstract
Abstract A circuit is disclosed for the generation of multi-level digital waveforms. The basic circuit, with some additions, is also capable of generating two or more of such waveforms, which have determinable phase relationships.
Inventors
- 👤 A Dodson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:15
CPC Classifications
H; H03; H03B; H03B27/00; H03K; H03K4/00; H03K4/02; H03K4/026
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
140 words
A circuit for generating a multilevel digital waveform comprising: a shift register; clock means for sequentially advancing the state of said shift register, means for decoding a plurality of states of said shift register, and switching means responsive to said decoding means for controlling circuit elements to vary the value of a voltage and/or a current in an electrical circuit, and yield said digital waveform across an intermediate output; the improvement comprising: a transistor bridge having one pair of opposite terminals connected across said intermediate output, and the other pair of opposite terminals for connection to a load, and a bistable flip flop responsive to a selected output of said decoding means, for controlling the conduction path in said transistor bridge, thereby altering the current direction through said load upon occurrence of a change in state of said flip flop.
Claim 2
Dependent Claim
140 words
A circuit for generating a multilevel digital waveform comprising: a shift register; clock means for sequentially advancing the state of said shift register, means for decoding a plurality of states of said shift register, and switching means responsive to said decoding means for controlling circuit elements to vary the value of a voltage and/or a current in an electrical circuit, and yield said digital waveform across an intermediate output; the improvement comprising: a transistor bridge having one pair of opposite terminals connected across said intermediate output, and the other pair of opposite terminals for connection to a load, and a bistable flip flop responsive to a selected output of said decoding means, for controlling the conduction path in said transistor bridge, thereby altering the current direction through said load upon occurrence of a change in state of said flip flop.
Claim 3
Dependent Claim
140 words
A circuit for generating a multilevel digital waveform comprising: a shift register; clock means for sequentially advancing the state of said shift register, means for decoding a plurality of states of said shift register, and switching means responsive to said decoding means for controlling circuit elements to vary the value of a voltage and/or a current in an electrical circuit, and yield said digital waveform across an intermediate output; the improvement comprising: a transistor bridge having one pair of opposite terminals connected across said intermediate output, and the other pair of opposite terminals for connection to a load, and a bistable flip flop responsive to a selected output of said decoding means, for controlling the conduction path in said transistor bridge, thereby altering the current direction through said load upon occurrence of a change in state of said flip flop.
Claim 4
Dependent Claim
140 words
A circuit for generating a multilevel digital waveform comprising: a shift register; clock means for sequentially advancing the state of said shift register, means for decoding a plurality of states of said shift register, and switching means responsive to said decoding means for controlling circuit elements to vary the value of a voltage and/or a current in an electrical circuit, and yield said digital waveform across an intermediate output; the improvement comprising: a transistor bridge having one pair of opposite terminals connected across said intermediate output, and the other pair of opposite terminals for connection to a load, and a bistable flip flop responsive to a selected output of said decoding means, for controlling the conduction path in said transistor bridge, thereby altering the current direction through said load upon occurrence of a change in state of said flip flop.
References Cited (Backward Citations)
US3124707A
Cited
US3292150A
Cited
US3335293A
Cited
US3356956A
Cited
US3500215A
Cited
US3521185A
Cited
US3659207A
Cited
US3651338A
Cited
US3659048A
Cited
US3657657A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-30 | 1976-07-31 | 1977-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-30 | 1980-07-31 | 1981-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-30 | 1984-07-31 | 1985-01-30 | $7700.00 | Window Closed / Lapsed |