Semiconductor thermal protection

Claim 2

A thermally protected semiconductor device, comprising: a plurality of semiconductor layers for passing therethrough a Flow of current which undesirably produces heating, electrode means for electrically contacting at least one of said semiconductor layers to vary said current flow under control of an external signal, variable impedance means having a temperature responsive impedance value, and mounting means for mounting said impedance means between said at least one semiconductor layer and said electrode means to substantially decrease said current flow through said semiconductor layers when a critical temperature is exceeded.

Claim 3

The semiconductor device of claim 1 wherein said impedance means has a positive temperature coefficient of impedance in which the impedance value substantially increases when said critical temperature is exceeded, and said mounting means mounts said impedance means in series with said at least one semiconductor layer to substantially decrease the strength of said signal and thereby decrease said current flow through said semiconductor layers.

Claim 4

The semiconductor device of claim 2 wherein said impedance means is composed of polycrystalline ceramic material with traces of impurity ions and has a transition temperature above which the impedance thereof increases nonlinearly to values greatly in excess of the impedance variations below said transition temperature.

Claim 5

The semiconductor device of claim 2 wherein said plurality of semiconductor layers comprise at least four layers forming a thyristor having a pair of main electrodes through which current flows under control of a gate signal at a gate electrode corresponding to said electrode means, and said mounting means mounts said impedance means in series with said gate electrode to prevent triggering of said thyristor when said critical temperature is exceeded.

Claim 6

The semiconductor device of claim 2 wherein said mounting means includes first metal surface means affixed to said one semiconductor layer, said impedance means contacts said first metal surface means, second metal surface means affixed to said impedance means and spaced from said first metal surface means, and terminal means connected to said second metal surface means for external circuit connection to the electrode means of said semiconductor device.

Claim 7

The semiconductor device of claim 5 including heat sink means thermally coupled to a different one of said plurality of semiconductor layers to dissipate the heating resulting from current flow.

Claim 8

A thermally protected semiconductor device, comprising: a plurality of first semiconductor layers for passing therethrough a flow of current which undesirably produces heating, electrode means for electrically contacting at least one of said first semiconductor layers to vary said current flow under control of a signal, variable impedance means having a temperature responsive impedance value including resistance means having a resistance value which changes when a critical temperature is exceeded, and a plurality of second semiconductor layers for passing current therethrough under control of a signal at a control electrode, first mounting means for thermally mounting said resistance means in heat transfer contact with said first semiconductor layers and electrically mounting said resistance means to said control electrode, and second mounting means for mounting said second semiconductor layers to said electrode means to substantially decrease said current flow through said first semiconductor layers when said critical temperature is exceeded.

Claim 9

A thermally protected semiconductor device, comprising: a plurality of first semiconductor layers for passing therethrough a flow of current which undesirably produces heating, electrode means for electrically contacting at least one of said first semiconductor layers to vary said current flow under control of a signal, variable impedance means having a temperature responsive impedance value including resistance means having a resistance value which changes when a critical temperature is exceeded, and a plurality of second semiconductor layers for passing current therethrough under control of a signal at a control electrode, first mounting means for thermally mounting said resistance means in heat transfer contact with said first semiconductor layers and electrically mounting said resistance means to said control electrode, and second mounting means for mounting said second semiconductor layers to said electrode means to substantially decrease said current flow through said first semiconductor layers when said critical temperature is exceeded.

Claim 10

The semiconductor device of claim 7 wherein said resistance means has a positive temperature coefficient produced by polycrystalline material having a Curie point near said critical temperature.

Claim 11

The semiconductor device of claim 7 wherein said plurality of second semiconductor layers comprise at least four layers of alternate P-type and N-type semiconductor material forming a thyristor, gate terminal means connected to one of said at least four layers to control the switching of said thyristor bEtween substantially nonconducting and substantially conducting states, said first mounting means electrically connecting said gate terminal means to said resistance means.

Claim 12

The semiconductor device of claim 7 wherein said plurality of second semiconductor layers comprise at least three alternate P and N type layers forming transistor means, said resistance means being connected by said first mounting means to bias said transistor means.

Claim 13

The semiconductor device of claim 10 wherein said first semiconductor layers are responsive to relatively positive and negative signals to produce relatively positive and negative current flow therethrough, and said plurality of second semiconductor layers includes a pair of three alternate P and N type layers forming a first and a second transistor of complementary types.

Claim 14

The semiconductor device of claim 7 wherein said impedance means has a substantial change in impedance value when the temperature thereof exceeds a transition temperature, said transition temperature being selected to be less than said critical temperature to compensate for a temperature tracking lag.

Claim 15

A thermally protected semiconductor device having a plurality of terminals for external circuit connection, comprising: a plurality of semiconductor layers for passing therethrough a flow of current which undesirably produces heating, at least one of said semiconductor layers defining a control area for varying the flow of current through said plurality of semiconductor layers in response to the value of a resistance in contact with said control area, base means for mounting said semiconductor layers and said plurality of terminals, variable resistance means having a temperature responsive resistance value, thermal protection means for mounting said variable resistance means in contact with said control area to substantially vary the resistance value thereof when a critical temperature is exceeded, and lead means for connecting said plurality of terminals to different ones of said plurality of semiconductor layers.

Claim 16

A thermally protected semiconductor device having a plurality of terminals for external circuit connection, comprising: a plurality of semiconductor layers for passing therethrough a flow of current which undesirably produces heating, at least one of said semiconductor layers defining a control area for varying the flow of current through said plurality of semiconductor layers in response to the value of a resistance in contact with said control area, base means for mounting said semiconductor layers and said plurality of terminals, variable resistance means having a temperature responsive resistance value, thermal protection means for mounting said variable resistance means in contact with said control area to substantially vary the resistance value thereof when a critical temperature is exceeded, and lead means for connecting said plurality of terminals to different ones of said plurality of semiconductor layers.

Claim 17

The semiconductor device of claim 13 wherein said plurality of semiconductor layers comprise at least four layers forming a thyristor, said plurality of terminals includes two main terminals and one gate terminal, said lead means connects said gate terminal to said control area and said two main electrodes to spaced layers, whereby said variable resistance means prevents triggering of said thyristor when said critical temperature is exceeded.

Claim 18

The semiconductor device of claim 13 wherein said variable resistance means comprises a pair of spaced surface means with temperature coefficient resistance material located therebetween, one of said surface means abutting said control area and being substantially the same size as the control area, and said lead means includes a metal bridge for connecting the remaining surface means to one of said terminals.

Claim 19

The semiconductor device of claim 15 wherein said remaining surface means is of a size substantially equal to said surface means abutting said control area, and said bridge means abutting said remaining surface means is of a size substantially less than said remaining surface means.

Claim 20

The semiconductor device of claim 13 wherein said variable resistance means is composed of polycrystalline ceramic material with traces of impurity ions and has a positive temperature coefficient with a transition temperature above which the resistance thereof increases nonlinearly to values greatly in excess of values below said transition temperature, and said lead means mounts one of said terminals to said variable resistance means to position said polycrystalline ceramic material in series with said one terminal.