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US3707767A
Expired / Lapsed
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Matrix with integrated semiconductors for dead memory
Assignee: Alcatel Lucent SAS
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Filing: 1970-06-26
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Granted: 1973-01-02
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Expires: 1990-06-26
Abstract
Abstract Process of manufacturing a matrix with integrated semiconductors for a dead memory, comprising semiconductor components included in the intersections of lines-columns of a network, which are adapted to being subjected to an electric test between line and column. The process consists in making on the one hand each of the columns, or lines, and on the other hand at least one of the regions of the components in the form of a pair of demi-columns, or half-columns, and demi-components, or half-components.
Inventors
- 👤 J Quevrin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:08
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C17/00; G11C17/08; G11C17/14; G11C17/16; G11C29/83; G11C29/832
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
323 words
A process for manufacturing a read-only memory, comprising the steps of: a. providing, on a substrate, a plurality of semiconductive components, each with at least one semiconductive junction between a first and a second region of opposite conductivity type; b. disposing, on said substrate, a succession of conductive columns insulated from each other, said columns adjacent and insulated from each other being a lower rank column and an upper rank column, in order that each of the components will be located between a lower rank column and an upper rank column; c. connecting said first region of each of said components to said lower rank column and to said upper rank column through a first and a second destructible connector, respectively; d. disposing, on said substrate, a succession of conductive lines insulated from each other and from said columns; e. connecting the second region of each of said components to one of said conductive lines in order that the several components connected to the same column by said first and second destructible connectors, respectively, will be connected to several respective lines, the number of these components being equal to the number of the several lines; f. detecting which of said components are useful and which of said components are not useful and classifying said components according to useful and non-useful components; g. destroying said first and second destructible connectors of each of said non-useful components; h. destroying one of said first and second destructible connectors of each of said useful components in order that the number of said useful components remaining connected through the said destructible connectors to said some of said columns will be equal to the number of said lines, said some of said columns corresponding to useful columns; and i. destroying, for some of said useful components connected to said useful columns, that destructible connector which is not destroyed during step (h) in order to record information in said memory.
Claim 2
Dependent Claim
323 words
A process for manufacturing a read-only memory, comprising the steps of: a. providing, on a substrate, a plurality of semiconductive components, each with at least one semiconductive junction between a first and a second region of opposite conductivity type; b. disposing, on said substrate, a succession of conductive columns insulated from each other, said columns adjacent and insulated from each other being a lower rank column and an upper rank column, in order that each of the components will be located between a lower rank column and an upper rank column; c. connecting said first region of each of said components to said lower rank column and to said upper rank column through a first and a second destructible connector, respectively; d. disposing, on said substrate, a succession of conductive lines insulated from each other and from said columns; e. connecting the second region of each of said components to one of said conductive lines in order that the several components connected to the same column by said first and second destructible connectors, respectively, will be connected to several respective lines, the number of these components being equal to the number of the several lines; f. detecting which of said components are useful and which of said components are not useful and classifying said components according to useful and non-useful components; g. destroying said first and second destructible connectors of each of said non-useful components; h. destroying one of said first and second destructible connectors of each of said useful components in order that the number of said useful components remaining connected through the said destructible connectors to said some of said columns will be equal to the number of said lines, said some of said columns corresponding to useful columns; and i. destroying, for some of said useful components connected to said useful columns, that destructible connector which is not destroyed during step (h) in order to record information in said memory.
Claim 3
Dependent Claim
202 words
A process according to claim 1, wherein each of said first regions comprise first and second half regions insulated from each other and being of the same conductivity type, each forming a semiconductive junction with said second region, said columns comprise a first and a second half-column, each of which is conductive, and is adjacent and insulated from another respective half-column, each of said components being located between the half of a column corresponding to a lower rank column and the half of a column corresponding to an immediately adjacent upper rank column, and wherein step (c) comprises for each of said components, the first destructible connector connects the first half region to the second half-column of said lower rank column and the second destructible connector connects said second half region to the first half column of said upper rank column, step (f) comprises classifying each of said components subsequent to the detection of the electrical current flowing between the line connected to a respective component and at least one of the halF columns connected to the component, and, furthermore, including an additional step (j) carried out subsequent to step (f), which comprises connecting two of the half columns to each other.
Claim 4
Dependent Claim
12 words
A process according to claim 1, wherein said destructible connectors are fuses.
Claim 5
Dependent Claim
33 words
A process according to claim 1, wherein each of said components comprises a transistor, having one common collector, said first regions correspond to emitter regions and said second regions correspond to base regions.
References Cited (Backward Citations)
US2994121A
Cited
US2982002A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-02 | 1976-07-03 | 1977-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-02 | 1980-07-03 | 1981-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-02 | 1984-07-03 | 1985-01-02 | $7700.00 | Window Closed / Lapsed |