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US3707622A
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US
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Digital serial arithmetic unit
Assignee: Omron Corp
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Filing: 1970-12-14
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Granted: 1972-12-26
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Expires: 1990-12-14
Abstract
Abstract An electronic system for use in calculating machines comprises a plurality of serial shift registers, an appropriate number of gates and a single serial full adder. This electronic system is adapted to perform the essential arithmetic operations in the calculator in a simple manner without necessitating a large number of components.
Inventors
- 👤 Isao Hatano
- 👤 Akira Nagano
- 👤 Kenzi Yosimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 11:40
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/491; G06F7/492; G06F7/493; G06F7/494; G06F7/495; G06F15/00; G06F15/02
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
270 words
A system for use in an electronic calculator comprising: first means for supplying input pulses to said system; a first serial shift register; a first gate circuit, coupled to the output of said first means, for gating the pulses generated thereby into said first serial shift register; a second serial shift register; a second gate circuit, coupled between said first and second serial shift registers, for gating the contents of said first serial shift register into said second serial shift register; a full adder circuit; a third gate circuit, coupled between said second serial shift register and a first input of said full adder circuit for gating the contents of said second serial shift register to said full adder circuit; a third serial shift register; a fourth gate circuit, coupled between said full adder circuit and said third serial shift register, for gating the output of said full adder circuit into said third serial shift register; a fifth gate circuit, coupled between said third serial shift register and a second input of said full adder circuit, for gating the contents of said third serial shift register to said full adder circuit; a sixth gate circuit, coupled between said full adder circuit and said first serial shift register, for gating the output of said full adder circuit into said first serial shift register; and second means, coupled to said second input and a third input of said full adder circuit, respectively, for supplying binary coded pulses representative of the decimal numbers +5 and +1 to said full adder circuit for complementation when the arithmetic operation of subtraction is to be performed.
Claim 2
Independent Claim
270 words
A system for use in an electronic calculator comprising: first means for supplying input pulses to said system; a first serial shift register; a first gate circuit, coupled to the output of said first means, for gating the pulses generated thereby into said first serial shift register; a second serial shift register; a second gate circuit, coupled between said first and second serial shift registers, for gating the contents of said first serial shift register into said second serial shift register; a full adder circuit; a third gate circuit, coupled between said second serial shift register and a first input of said full adder circuit for gating the contents of said second serial shift register to said full adder circuit; a third serial shift register; a fourth gate circuit, coupled between said full adder circuit and said third serial shift register, for gating the output of said full adder circuit into said third serial shift register; a fifth gate circuit, coupled between said third serial shift register and a second input of said full adder circuit, for gating the contents of said third serial shift register to said full adder circuit; a sixth gate circuit, coupled between said full adder circuit and said first serial shift register, for gating the output of said full adder circuit into said first serial shift register; and second means, coupled to said second input and a third input of said full adder circuit, respectively, for supplying binary coded pulses representative of the decimal numbers +5 and +1 to said full adder circuit for complementation when the arithmetic operation of subtraction is to be performed.
Claim 3
Independent Claim
362 words
A system for use in an electronic calculator comprising: first means for supplying input pulses to said system; a first serial shift register; a first gate circuit, coupled to the output of said first means, for gating the pulses generated thereby into said first serial shift register; a second serial shift register; a second gate circuit, coupled between said first and second serial shift registers, for gating the contents of said first serial shift register into said second serial shift register; a full adder circuit; a third gate circuit, coupled between said second serial shift register and a first input of said full adder circuit for gating the contents of said second serial shiFt register to said full adder circuit; a third serial shift register; a fourth gate circuit, coupled between said full adder circuit and said third serial shift register, for gating the output of said full adder circuit into said third serial shift register; a fifth gate circuit, coupled between said third serial shift register and a second input of said full adder circuit, for gating the contents of said third serial shift register to said full adder circuit; a sixth gate circuit, coupled between said full adder circuit and said first serial shift register, for gating the output of said full adder circuit into said first serial shift register; and second means, coupled to said second input and a third input of said full adder circuit, respectively, for supplying binary coded pulses representative of the decimal numbers +5 and +1 to said full adder circuit for complementation when the arithmetic operation of subtraction is to be performed, said second serial shift register comprises first and second stages connected in series, said first stage being connected to the output of said second gate circuit, the output of said second stage being connected to said third gate circuit, and further including third means, coupled to the output of said second stage of said second serial shift register, for feeding back the output of said second stage to at least one of the circuit elements consisting of said first serial shift register and said first stage of said second serial shift register.
Claim 4
Independent Claim
362 words
A system for use in an electronic calculator comprising: first means for supplying input pulses to said system; a first serial shift register; a first gate circuit, coupled to the output of said first means, for gating the pulses generated thereby into said first serial shift register; a second serial shift register; a second gate circuit, coupled between said first and second serial shift registers, for gating the contents of said first serial shift register into said second serial shift register; a full adder circuit; a third gate circuit, coupled between said second serial shift register and a first input of said full adder circuit for gating the contents of said second serial shiFt register to said full adder circuit; a third serial shift register; a fourth gate circuit, coupled between said full adder circuit and said third serial shift register, for gating the output of said full adder circuit into said third serial shift register; a fifth gate circuit, coupled between said third serial shift register and a second input of said full adder circuit, for gating the contents of said third serial shift register to said full adder circuit; a sixth gate circuit, coupled between said full adder circuit and said first serial shift register, for gating the output of said full adder circuit into said first serial shift register; and second means, coupled to said second input and a third input of said full adder circuit, respectively, for supplying binary coded pulses representative of the decimal numbers +5 and +1 to said full adder circuit for complementation when the arithmetic operation of subtraction is to be performed, said second serial shift register comprises first and second stages connected in series, said first stage being connected to the output of said second gate circuit, the output of said second stage being connected to said third gate circuit, and further including third means, coupled to the output of said second stage of said second serial shift register, for feeding back the output of said second stage to at least one of the circuit elements consisting of said first serial shift register and said first stage of said second serial shift register.
Claim 5
Independent Claim
319 words
A system for use in an electronic calculator comprising: first means for supplying input pulses to said system; a first serial shift register; a first gate circuit, coupled to the output of said first means, for gating the pulses generated thereby into said first serial shift register; a second serial shift register; a second gate circuit, coupled between said first and second serial shift registers, for gating the contents of said first serial shift register into said second serial shift register; a full adder circuit; a third gate circuit, coupled between said second serial shift register and a first input of said full adder circuit for gating the contents of said second serial shift register to said full adder circuit; a third serial shift register; a fourth gate circuit, coupled between said full adder circuit and said third serial shift register, for gating the output of said full adder circuit into said third serial shift register; a fifth gate circuit, coupled between said third serial shift register and a second input of said full adder circuit, for gating the contents of said third serial shift register to said full adder circuit; a sixth gate circuit, coupled between said full adder circuit and said first serial shift register, for gating the output of said full adder circuit into said first serial shift register; second means, coupled to said second input and a third input of said full adder circuit, respectively, for supplying binary coded pulses representative of the decimal numbers +5 and +1 to said full adder circuit for complementation when the arithmetic operation of subtraction is to be performed; and a fourth serial shift register connected to the output of said first serial shift register and a seventh gate circuit connected between said fourth serial shift register and said second serial shift register, for gating the contents of said fourth serial shift register into said second serial shift register.
Claim 6
Independent Claim
319 words
A system for use in an electronic calculator comprising: first means for supplying input pulses to said system; a first serial shift register; a first gate circuit, coupled to the output of said first means, for gating the pulses generated thereby into said first serial shift register; a second serial shift register; a second gate circuit, coupled between said first and second serial shift registers, for gating the contents of said first serial shift register into said second serial shift register; a full adder circuit; a third gate circuit, coupled between said second serial shift register and a first input of said full adder circuit for gating the contents of said second serial shift register to said full adder circuit; a third serial shift register; a fourth gate circuit, coupled between said full adder circuit and said third serial shift register, for gating the output of said full adder circuit into said third serial shift register; a fifth gate circuit, coupled between said third serial shift register and a second input of said full adder circuit, for gating the contents of said third serial shift register to said full adder circuit; a sixth gate circuit, coupled between said full adder circuit and said first serial shift register, for gating the output of said full adder circuit into said first serial shift register; second means, coupled to said second input and a third input of said full adder circuit, respectively, for supplying binary coded pulses representative of the decimal numbers +5 and +1 to said full adder circuit for complementation when the arithmetic operation of subtraction is to be performed; and a fourth serial shift register connected to the output of said first serial shift register and a seventh gate circuit connected between said fourth serial shift register and said second serial shift register, for gating the contents of said fourth serial shift register into said second serial shift register.
Claim 7
Dependent Claim
24 words
A system according to claim 3, wherein each of said first, second and third serial shift registers is a gate controlled recirculating shift register.
Claim 8
Dependent Claim
95 words
A system according to claim 3, wherein said second serial shift register comprises first and second stages connected in series, said first stage being connected to the outputs of said second and seventh gate circuits, the output of said second stage being connected to said third gate cIrcuit, and further including third means, coupled to the output of said second stage, for feeding back the output of said second stage to at least one of the circuit elements consisting of said first serial shift register and said first stage of said second serial shift register.
Claim 9
Dependent Claim
69 words
A system according to claim 5, wherein said third means comprises eighth and ninth gate circuits, respectively connected between the output of said second stage of said second serial shift register and said first serial shift register and said first stage of said second serial shift register, and further including a 10th gate circuit for feeding back the output of said third serial shift register to the input thereof.
Claim 10
Dependent Claim
104 words
A system according to claim 6, further including an 11th gate circuit, coupled between the output of said first stage of said second serial shift register and said first and third serial shift registers, for gating the contents of said first stage of said second serial shift register into said first and third serial shift registers, and further including a 12th gate circuit connected between the output of said third serial shift register and said first input of said full adder circuit, for gating the contents of said third serial shift register to said full adder circuit, in addition to said fifth gate circuit.
Claim 11
Dependent Claim
24 words
A system according to claim 7, wherein each of said first, second and third serial shift registers is a gate controlled recirculating shift register.
Claim 12
Dependent Claim
31 words
A system according to claim 7, further including a gated inverter circuit coupled between the output of said full adder and the inputs of said first and third serial shift register.
Claim 13
Dependent Claim
26 words
A system according to claim 9, further including a one bit delay circuit gated between the output of said full adder and said third input thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-12-26 | 1976-06-26 | 1976-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-12-26 | 1980-06-26 | 1980-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-12-26 | 1984-06-26 | 1984-12-26 | $7700.00 | Window Closed / Lapsed |