Pulse repetition frequency detection and lock-on system

Claim 1

A pulse repetition frequency detection and lock on system which comprises: a. a track loop circuit which includes: 1. a flip-flop circuit for receiving a train of incoming pulses which may have various pulse repetition frequencies; 2. a variable period one-shot circuit coupled to the flip-flop circuit to be driven by a train of output pulses from the flip-flop circuit; and 3. an integrator circuit coupled to the flip-flop and one-shot circuits for being driven in an increasing voltage direction by the output of the flip-flop circuit and in a decreasing voltage direction by the output of the one-shot circuit; 4. the output of the integrator circuit being fed back to the one-shot circuit to complete the track loop, so that upon the track loop being locked on to the train of incoming pulses, the voltage of the integrator circuit output is a linear function of the period of the pulse repetition frequency of the train of incoming pulses; b. an error detector circuit coupled to the track loop for comparing the difference between the flip-flop circuit period and the one-shot circuit period, and for putting out enable and disable pulses logically; c. a pulse repetition frequency detector circuit coupled to the error detector circuit for processing the enable and disable output pulses from the error detector circuit and determining when a proper ratio of enable to disable pulses has been obtained; d. an AND gate coupled to the track loop, error detector and pulse repetition frequency detector circuits so that the AND gate is disabled by the output of the pulse repetition frequency detector circuit until a majority of one pulse repetition frequency is present in the train of incoming pulses so that the output of the pulse repetition frequency detector circuit increases and thus enables a part of the AND gate; and e. and a end-shot circuit coupled to the track loop circuit and the AND gate to enable the AND gate when a majority of one pulse repetition frequency is present in the train of incoming pulses so that the AND gate is enabled prior to the next expected pulse repetition frequency input in the train of incoming pulses and thus locks the system onto the desired pulse repetition frequency of the train of incoming pulses.