Arrangement for translating a train of pulses into logic words

Claim 2

An arrangement for translating two spaced sets of pulses transmitted in a train, which represent a letter-number identification of a record selection to be played in a coinoperated phonograph, into three logic words of four data bits each, which represent a three digit numerical identification of the record selection, comprising: first gate means having the train of pulses applied thereto; second gate means having the train of pulses applied thereto; transfer means adapted to open said first gate means for only one of the sets of pulses in the train and to open said second gate means for only the other set of pulses in the train; a first binary counter adapted to accumulate the pulses passing through said first gate means and preserve the total thereof; a first flip-flop and a second binary counter adapted to accumulate the pulses passing through said second gate means and preserve the total thereof; timing control means actuated after termination of the train of pulses to cause the signals stored in said first flip-flop to be conveyed to the data lines first in a time sequence, the pulse totals in said first binary counter to be conveyed to the data lines second, and the post totals in said second binary counter to be conveyed to the data lines last; first distributing means to convey the pulse totals in said first binary counter to appropriate data output lines; and second distributing means to convey the pulse totals in said second binary counter to appropriate data output lines.

Claim 3

An arrangement as claimed in claim 1 wherein said first and second distributing means comprise first and second decoder circuits, respectively.

Claim 4

An arrangement as claimed in claim 2 wherein said timing control means comprises a third binary counter and a third decoder circuit.

Claim 5

An arrangement as claimed in claim 3 and further comprising a clock circuit activated upon termination of the train of pulses to actuate said third binary counter.

Claim 6

An arrangement as claimed in claim 1 and further comprising reset means to clear all flip-flops and counters after the signal stored in said first flip-flop and the pulse totals preserved in said first and second binary counters have been distributed to the appropriate data lines.

Claim 7

An arrangement as claimed in claim 1 wherein said transfer means comprises a second flip-flop.

Claim 8

An arrangement for translating a train of pulses, which is divided into a first set of pulses and a second set of pulses, into three four-bit logic words comprising: a first logic gate to which the train of pulses is applied, said first logic gate normally open to permit passage of the first set of pulses therethrough; a second logic gate to which the train of pulses is applied, said second logic gate normally closed to prevent passage of the first set of pulses therethrough; a transfer flip-flop actuated after the first set of pulses has passed through said first logic gate to close said first logic gate to prevent passage of the second set of pulses therethrough and open said second logic gate to permit passage of the second set of pulses therethrough; a first binary counter adapted to count and store pulses passed through said first logic gate; a first flip-flop and a second binary counter adapted to count and store pulses passed through said second logic gate; a third binary counter actuated by the envelopes of the first and second sets of pulses; a clock circuit, said clock Circuit being activated upon actuation of said third binary counter by the envelope of the second set of pulses to automatically actuate said third binary counter with a series of pulses; a third decoder adapted to convert the outputs of said third binary counter to signals representing numerical values, upon said third decoder reaching a first predetermined numerical count the outputs of said first-flip being conveyed to appropriate data lines; a first decoder adapted to convert the outputs of said first binary circuit to signals representing numerical values and to direct the resulting signals to appropriate data lines, the outputs of said first binary counter being applied to said first decoder upon said third decoder reaching a second predetermined numerical count; a second decoder adapted to convert the outputs of said second binary circuit to signals representing numerical values and to direct the resulting signals to appropriate data lines, the outputs of said second binary counter being applied to said second decoder upon said third decoder reaching a third predetermined numerical count; and a reset circuit actuated upon said third decoder reaching a fourth predetermined numerical count to clear all of said flip-flops and binary counters.

Claim 9

An arrangement for translating a train of pulses, which is divided into a first set of pulses and a second set of pulses, into three four-bit logic words comprising: a first logic gate to which the train of pulses is applied, said first logic gate normally open to permit passage of the first set of pulses therethrough; a second logic gate to which the train of pulses is applied, said second logic gate normally closed to prevent passage of the first set of pulses therethrough; a transfer flip-flop actuated after the first set of pulses has passed through said first logic gate to close said first logic gate to prevent passage of the second set of pulses therethrough and open said second logic gate to permit passage of the second set of pulses therethrough; a first binary counter adapted to count and store pulses passed through said first logic gate; a first flip-flop and a second binary counter adapted to count and store pulses passed through said second logic gate; a third binary counter actuated by the envelopes of the first and second sets of pulses; a clock circuit, said clock Circuit being activated upon actuation of said third binary counter by the envelope of the second set of pulses to automatically actuate said third binary counter with a series of pulses; a third decoder adapted to convert the outputs of said third binary counter to signals representing numerical values, upon said third decoder reaching a first predetermined numerical count the outputs of said first-flip being conveyed to appropriate data lines; a first decoder adapted to convert the outputs of said first binary circuit to signals representing numerical values and to direct the resulting signals to appropriate data lines, the outputs of said first binary counter being applied to said first decoder upon said third decoder reaching a second predetermined numerical count; a second decoder adapted to convert the outputs of said second binary circuit to signals representing numerical values and to direct the resulting signals to appropriate data lines, the outputs of said second binary counter being applied to said second decoder upon said third decoder reaching a third predetermined numerical count; and a reset circuit actuated upon said third decoder reaching a fourth predetermined numerical count to clear all of said flip-flops and binary counters.

Claim 10

An arrangement as claimed in claim 7 wherein said transfer flip-flop is actuated by the envelopes of the sets of pulses.

Claim 11

An arrangement as claimed in claim 7 wherein said first predetermined count of said third decoder is three, said second predetermined count is five, said third predetermined count is seven and said fourth predetermined count is zero.

Claim 12

An arrangement as claimed in claim 7 wherein said first and second logic gates are NOR gates.

Claim 13

An arrangement as claimed in claim 7 and further comprising a logic circuit adapted to convey signals to appropriate data lines when said second decoder reaches a numerical count of zero.