Patent US3705392A successfully refreshed from Google Patents.
US3705392A
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Mos dynamic memory
Assignee: Texas Instruments Inc
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Filing: 1971-09-07
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Granted: 1972-12-05
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Expires: 1991-09-07
Abstract
Abstract An MOS memory array has a number of memory cells fabricated on a single chip. A refresh control sensor senses the temperature of the environment of the MOS memory array. The MOS memory array is refreshed depending upon the environmental temperature of the memory array. This allows a minimum power consumption in the standby mode of the MOS dynamic memory.
Inventors
- 👤 Daren Ray Appelt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:47
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
33 words
In an MOS memory array comprising means for sensing the temperature of said MOS memory array and means responsive to said temperature sensing means for initiating a refresh of said MOS memory array.
Claim 2
Dependent Claim
33 words
In an MOS memory array comprising means for sensing the temperature of said MOS memory array and means responsive to said temperature sensing means for initiating a refresh of said MOS memory array.
Claim 3
Dependent Claim
39 words
The invention claimed in claim 1 having a flip-flop reset by said pulse generator and set by said temperature-dependent timer when said temperature-dependent timer generates a refresh start pulse to start a refresh cycle in said MOS memory array.
Claim 4
Dependent Claim
115 words
In a MOS memory array comprising a pulse generator set when a refresh cycle in said MOS memory array is completed, a temperature-dependent timer reset by said pulse generator when a refresh cycle is completed, said temperature-dependent timer responsive to the completion of a refresh cycle in said MOS memory array to begin timing a new cycle, at least one thermistor having a negative temperature coefficient, a capacitor in said temperature-dependent timer, said capacitor charged according to the temperature of said MOS memory array sensEd by said thermistors, said temperature-dependent timer generating a refresh start pulse to start a refresh cycle in said MOS memory array when said capacitor is charged to a predetermined potential.
Claim 5
Dependent Claim
115 words
In a MOS memory array comprising a pulse generator set when a refresh cycle in said MOS memory array is completed, a temperature-dependent timer reset by said pulse generator when a refresh cycle is completed, said temperature-dependent timer responsive to the completion of a refresh cycle in said MOS memory array to begin timing a new cycle, at least one thermistor having a negative temperature coefficient, a capacitor in said temperature-dependent timer, said capacitor charged according to the temperature of said MOS memory array sensEd by said thermistors, said temperature-dependent timer generating a refresh start pulse to start a refresh cycle in said MOS memory array when said capacitor is charged to a predetermined potential.
Claim 6
Dependent Claim
46 words
In an MOS memory array comprising means for sensing and temperature of said MOS memory array, a temperature-dependent timer, said temperature-dependent timer responsive to said temperature sensing means for initiating a refresh cycle in said MOS memory array when said temperature-dependent timer reaches a predetermined level.
Claim 7
Dependent Claim
46 words
In an MOS memory array comprising means for sensing and temperature of said MOS memory array, a temperature-dependent timer, said temperature-dependent timer responsive to said temperature sensing means for initiating a refresh cycle in said MOS memory array when said temperature-dependent timer reaches a predetermined level.
Claim 8
Dependent Claim
90 words
In an MOS memory array having a temperature-dependent timer, said temperature-dependent timer having a first thermistor and a second thermistor to sense the temperature of the environment of said MOS memory array, a timing capacitor in said temperature-dependent timer being capable of being charged to a predetermined reference level dependent upon the temperature sensed by said thermistors, said temperature-dependent timer generating a refresh enable pulse when said timing capacitor has been charged to said predetermined reference level, said refresh enable pulse starting a refresh cycle in said MOS memory array.
Claim 9
Dependent Claim
90 words
In an MOS memory array having a temperature-dependent timer, said temperature-dependent timer having a first thermistor and a second thermistor to sense the temperature of the environment of said MOS memory array, a timing capacitor in said temperature-dependent timer being capable of being charged to a predetermined reference level dependent upon the temperature sensed by said thermistors, said temperature-dependent timer generating a refresh enable pulse when said timing capacitor has been charged to said predetermined reference level, said refresh enable pulse starting a refresh cycle in said MOS memory array.
Claim 10
Dependent Claim
126 words
In an MOS memory array, a pulse generator, said pulse generator reset by the completion of a refresh cycle in said MOS memory array, a temperature-dependent timer, said temperature-dependent timer having at least one thermistor to sense the environment of said MOS memory array, said temperature-dependent timer having a timing capacitor, said timing capacitor charged to a predetermined reference level dependent upon the temperature sensed by said thermistors, said temperature-dependent timer producing a pulse when said timing capacitor is charged to said predetermined reference level, a refresh enable flip-flop, said refresh enable flip-flop set when said temperature-dependent timer produces an output pulse, said refresh enable flip-flop applying a refresh enable signal to said MOS memory array to start a refresh cycle in said MOS memory array.
Claim 11
Dependent Claim
126 words
In an MOS memory array, a pulse generator, said pulse generator reset by the completion of a refresh cycle in said MOS memory array, a temperature-dependent timer, said temperature-dependent timer having at least one thermistor to sense the environment of said MOS memory array, said temperature-dependent timer having a timing capacitor, said timing capacitor charged to a predetermined reference level dependent upon the temperature sensed by said thermistors, said temperature-dependent timer producing a pulse when said timing capacitor is charged to said predetermined reference level, a refresh enable flip-flop, said refresh enable flip-flop set when said temperature-dependent timer produces an output pulse, said refresh enable flip-flop applying a refresh enable signal to said MOS memory array to start a refresh cycle in said MOS memory array.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-12-05 | 1976-06-05 | 1976-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-12-05 | 1980-06-05 | 1980-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-12-05 | 1984-06-05 | 1984-12-05 | $7700.00 | Window Closed / Lapsed |