Patent US3705359A successfully refreshed from Google Patents.
US3705359A
Expired / Lapsed
US
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Pcm decoder with expansion characteristic
Assignee: TE Connectivity Germany GmbH
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Filing: 1971-03-08
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Granted: 1972-12-05
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Expires: 1991-03-08
Abstract
Abstract Incoming binary code words of n+m+1 bits, the highest-ranking of them being a polarity indicator, are fed to a first decoding stage which converts the lower-ranking n-bit group into a corresponding analog voltage of up to 2n incremental steps and, in the presence of at least one bit of logical value '''' 1'''' in the higher-ranking m-bit group, superimposes upon this analog voltage a fixed voltage of 2n incremental steps. A second decoding stage simultaneously receives the m-bit group and derives from it a stepdown factor, ranging from 0 to 2m, by which a switching circuit controlled by that stage divides the output of the first stage.
Inventors
- 👤 Werner Kappes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 04:33
CPC Classifications
H; H04; H04B; H04B14/00; H04B14/02; H04B14/04; H04B14/046; H04B14/048; H03; H03M; H03M1/00; H03M1/06; H03M1/0617
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
169 words
A pulse-code demodulator in a receiver for binary code words of a predetermined number of bits forming a lower-ranking n-bit group and a higher-ranking m-bit group, comprising: storage means for temporarily registering the bits of an incoming code word; a first decoding stage connected to said stage means for receiving both said groups therefrom, said first stage including an impedance network with individually switchable branches controlled by said lower-ranking group to generate a corresponding analog voltage composed of up to 2n incremental steps, said network being provided with a further switchable branch controlled by said higher-ranking group for superimposing upon said analog voltage of 2n incremental steps in the output of said first stage in the presence of any finite bit in the said higher-ranking group; a second decoding stage connected to said storage means for receiving said higher-ranking group therefrom; and weighting means controlled by said second stage from multiplying the output of said first stage by a factor proportional to the analog equivalent of said higher-ranking group.
Claim 2
Dependent Claim
169 words
A pulse-code demodulator in a receiver for binary code words of a predetermined number of bits forming a lower-ranking n-bit group and a higher-ranking m-bit group, comprising: storage means for temporarily registering the bits of an incoming code word; a first decoding stage connected to said stage means for receiving both said groups therefrom, said first stage including an impedance network with individually switchable branches controlled by said lower-ranking group to generate a corresponding analog voltage composed of up to 2n incremental steps, said network being provided with a further switchable branch controlled by said higher-ranking group for superimposing upon said analog voltage of 2n incremental steps in the output of said first stage in the presence of any finite bit in the said higher-ranking group; a second decoding stage connected to said storage means for receiving said higher-ranking group therefrom; and weighting means controlled by said second stage from multiplying the output of said first stage by a factor proportional to the analog equivalent of said higher-ranking group.
Claim 3
Dependent Claim
39 words
A demodulator as defined in claim 1 wherein said first stage further comprises switchover means in said network responsive to an additional bit, ranking above said m-bit group in a code work, for reversing the polarity of said output.
Claim 4
Dependent Claim
42 words
A demodulator as defined in claim 1 wherein said network includes an OR gate with input connections to respective parts of said storage means registering said m bits, said further branch being responsive to a control signal generated by said OR gate.
Claim 5
Dependent Claim
23 words
A demodulator as defined in claim 1 wherein said first stage comprises an operational amplifier with an inverting input connected to said network.
Claim 6
Dependent Claim
86 words
A demodulator as defined in claim 4 wherein said network comprises n+2 parallel resistances joined to said inverting input and having staggered magnitudes 2iR where i is an integer ranging from 0 through n+1, the largest resistance of magnitude 2n 1R being connected to a source of fixed reference potential, the smallest resistance of magnitude R being switchable into circuit in response to a finite bit in said higher-ranking group, the remaining resistances being switchable into circuit in response to respective bits in said lower-ranking group.
Claim 7
Dependent Claim
35 words
A demodulator as defined in claim 5, further comprising switchover means in said network responsive to an additional bit, ranking above said m-bit group in a code work, for reversing the polarity of said source.
Claim 8
Dependent Claim
22 words
A demodulator as defined in claim 5 wherein said operational amplifier has a feedback path with a series resistance of magnitude R/2.
Claim 9
Dependent Claim
64 words
A demodulator as defined in claim 4 wherein said network comprises a resistive ladder circuit of R/2R type with an arm of magnitude 2R connected to a source of fixed reference potential and with n+1 other arms of like magnitude 2R selectively connectable to said source in response to respective bits in said lower-ranking group and to a finite bit in said higher-ranking group.
Claim 10
Dependent Claim
41 words
A demodulator as defined in claim 4, further comprising an inverter ahead of said operational amplifier and switchover means in said network responsive to an additional bit, ranking above said m-bit group in a code word, for selectively short-circuiting said inverter.
Claim 11
Dependent Claim
157 words
A demodulator as defined in claim 1 wherein said weighting means comprises an impedance transformer of high input resistance and further comprises a potentiometer with 2m-1 series resistors, a high-voltage terminal connected to said first stage for energization thereby, aNd an opposite grounded terminal, said resistors forming 2m-2 taps between said terminals and having progressively decreasing magnitudes ranging from a value 2(2 3)r for the resistor nearest said high-voltage terminal to a value r between the two taps farthest from said high-voltage terminal, the resistor lying between said grounded terminal and the tap nearest thereto having the same magnitude r, said taps and said high-voltage terminal being selectively connectable to said impedance transformer under the control of said m bits, the tap nearest said grounded terminal being so connectable regardless of the logic value of the least significant bit of said higher-ranking group upon all the other bits of the latter group having the logical value 0.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-12-05 | 1976-06-05 | 1976-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-12-05 | 1980-06-05 | 1980-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-12-05 | 1984-06-05 | 1984-12-05 | $7700.00 | Window Closed / Lapsed |