Count display system

Claim 2

A count display system comprising a first count display device for counting and displaying numerals of lower orders of magnitude, a second count display device for counting and displaying numerals of higher orders of magnitude, a prescaler having a ratio of frequency division preset in accordance with said lower orders, first gate circuit means responsive to a gate control signal for supplying input signals to said prescaler for a predetermined time interval, second gate circuit means responsive to said gate control signal for supplying the output from said prescaler to said second count display device, reference pulse control means responsive to said gate control signal and the output from said prescaler for controlling a supply of reference pulses, means controlled by the output from said reference pulse control means for supplying said reference pulses to said prescaler, and means for supplying pulses of the number as the reference pulses supplied to said prescaler to said first count display device so as to calculate the difference between the limiting value of the frequency division of said prescaler and the value actually counted by utilizing said reference pulses whereby to display the value actually counted.

Claim 3

A count display system comprising a plurality of successive count display devices, a prescaler having a ratio of frequency division preset in accordance with the number of orders of magnitude to be displayed, first gate means responsive to a gate control signal for supplying input signals to said prescaler for a predetermined time interval, second gate circuit means responsive to said gate control signal for supplying the output from said prescaler to succeeding count display devices, reference pulse control means responsive to said gate control signal and the output from said prescaler for controlling a supply of reference pulses, means controlled by the output from said reference pulse control means for supplying said reference pulses to said prescaler, and means for supplying pulses of the same number as the reference pulses supplied to said prescaler to said count display devices, said prescaler including a plurality of serially connected frequency dividers of the ratio of frequency division of 1/2 each which are connected in the earlier stages of said prescaler and a plurality of serially connected frequency dividers of the ratio of frequency division of 1/5 each which are connected in series with said first mentioned frequency dividers in the later stages of said prescaLer, so that the difference between the limiting value of the frequency division of said prescaler and the value actually calculated is determined by utilizing said reference pulses, whereby to display the value actually counted.

Claim 4

A count display system comprising a plurality of successive count display devices, a prescaler having a ratio of frequency division preset in accordance with the number of orders of magnitude to be displayed, first gate means responsive to a gate control signal for supplying input signals to said prescaler for a predetermined time interval, second gate circuit means responsive to said gate control signal for supplying the output from said prescaler to succeeding count display devices, reference pulse control means responsive to said gate control signal and the output from said prescaler for controlling a supply of reference pulses, means controlled by the output from said reference pulse control means for supplying said reference pulses to said prescaler, and means for supplying pulses of the same number as the reference pulses supplied to said prescaler to said count display devices, said prescaler including a plurality of serially connected frequency dividers of the ratio of frequency division of 1/2 each which are connected in the earlier stages of said prescaler and a plurality of serially connected frequency dividers of the ratio of frequency division of 1/5 each which are connected in series with said first mentioned frequency dividers in the later stages of said prescaLer, so that the difference between the limiting value of the frequency division of said prescaler and the value actually calculated is determined by utilizing said reference pulses, whereby to display the value actually counted.

Claim 5

The count display circuit according to claim 2 wherein said count display devices comprise a plurality of serially connected decimal counting circuits for different orders of magnitude, a plurality of decoders for converting the outputs of respective decimal counting circuits into respective decimal numbers, a plurality of display units associated with respective decoders for displaying digits 0,9,8, . . . 2, 1 in response to the outputs 0,1,2 . . . 8, 9 of said decoders and a plurality of bistable circuits, each one of said bistable circuits being connected between two adjacent decimal counting circuits such that it is set by a signal firstly applied to the preceding decimal counting circuit and reset by the tenth signal applied to the preceding decimal counting circuit, said bistable circuit being adapted to send a signal to the succeeding decimal counting circuit with it is in its set condition.

Claim 6

The count display system according to claim 1 wherein each of said count display devices comprises a decimal counting circuit, a decoder connected to said decimal counting circuit for converting the outputs thereof into decimal numbers and a display unit for displaying said decimal numbers.

Claim 7

The count display system according to claim 2 wherein each of said count display devices comprises a decimal counting circuit, a decoder connected to said decimal counting circuit for converting the outputs thereof into decimal numbers and a display unit for displaying said decimal numbers.