Supervisory circuit for monitoring the formation and termination of interconnections in a time-division switch

Claim 2

In a time-division switch for forwarding data signals in individual time slots on an incoming data bus to selected outgoing ports as directed by address words in corresponding time slots on an address bus, a signaling circuit for inserting supplementary data signals into the data bus comprising, means for storing the supplementary data signals, means for producing accompanying address words, and means responsive to an idle time slot on the address bus for withdrawing a stored data signal from the storing means, for writing the produced address word accompanying the withdrawn data signal into the idle time slot on the address bus and for writing the withdrawn data signal into the corresponding time slot on the data bus.

Claim 3

In a time-division switch, a signaling circuit in accordance with claim 1 wherein each address bus time slot accommodates a flag bit indicating the presence of an address word in the time slot and the means responsive to an idle time slot includes means for monitoring the flat bit.

Claim 4

In a time-division switch for receiving data bytes in individual time slots on the incoming side of a data bus and forwarding the data bytes to selected outgoing ports by way of the outgoing side of the data bus as directed by address words in corresponding time slots on an address bus, an interface circuit for inserting supplementary data bytes onto the outgoing side of the data bus comprising, gate means interposed between the incoming side and the outgoing side of the data bus for passing bytes from the incoming side of the outgoing side thereof, means for producing and storing the supplementary data bytes, means for producing address words to accompany each of the stored data bytes, and means for detecting an idle time slot on the address bus and, in response thereto, for disabling the gate means, for withdrawing a stored data byte from the storing means, for writing the produced word accompanying the withdrawn byte into the idle time slot on the address bus and for writing the withdrawn data byte into the corresponding time slot on the outgoing side of the data bus.

Claim 5

In a time-division switch for receiving data bytes in individual time slots on the incoming side of a data bus and forwarding the data bytes to selected outgoing ports by way of the outgoing side of the data bus as directed by address words in corresponding time slots on an address bus, an interface circuit for inserting supplementary data bytes onto the outgoing side of the data bus comprising, gate means interposed between the incoming side and the outgoing side of the data bus for passing bytes from the incoming side of the outgoing side thereof, means for producing and storing the supplementary data bytes, means for producing address words to accompany each of the stored data bytes, and means for detecting an idle time slot on the address bus and, in response thereto, for disabling the gate means, for withdrawing a stored data byte from the storing means, for writing the produced word accompanying the withdrawn byte into the idle time slot on the address bus and for writing the withdrawn data byte into the corresponding time slot on the outgoing side of the data bus.

Claim 6

In a time-division switch, an interface circuit in accordance with claim 3 wherein the means for detecting an idle time slot includes means for monitoring a flag bit appearing in each time slot on the address bus, said monitoring means including means for enabling the gate means in response to the monitoring of a flag bit of one type and means for enabling the idle time slot detecting means in response to the monitoring of a flag bit of another type.

Claim 7

In a time-division switch for receiving data bytes in individual time slots on an incoMing data bus and applying the data bytes to selected time slots on time-division lines as directed by address words in time slots on an address bus, each address bus time slot corresponding to the data bus time slot accommodating the data byte directed by the address word, a supervisory signaling circuit for forwarding the bytes of a supervisory message to time slots on a predetermined time-division line, comprising, means for producing and storing successive bytes of the supervisory message, means for generating address words designating successive time slots on the predetermined line, and means responsive to detection of an idle time slot on the address bus for inserting a generated address word therein and inserting a stored message byte into the corresponding time slot on the data bus.

Claim 8

In a time-division switch for receiving data bytes in individual time slots on an incoMing data bus and applying the data bytes to selected time slots on time-division lines as directed by address words in time slots on an address bus, each address bus time slot corresponding to the data bus time slot accommodating the data byte directed by the address word, a supervisory signaling circuit for forwarding the bytes of a supervisory message to time slots on a predetermined time-division line, comprising, means for producing and storing successive bytes of the supervisory message, means for generating address words designating successive time slots on the predetermined line, and means responsive to detection of an idle time slot on the address bus for inserting a generated address word therein and inserting a stored message byte into the corresponding time slot on the data bus.

Claim 9

In a time-division switch, a supervisory signaling circuit in accordance with claim 5 wherein the means responsive to the detection of an idle time slot inserts successive ones of the bytes of the message onto the data bus and successive ones of the address words onto the address bus in response to the detection of successive ones of the idle time slots.

Claim 10

In a time-division switch, a supervisory signaling circuit in accordance with claim 6 wherein the means for generating the address words includes means for generating the address word designating a first one of the time slots on the predetermined line and means responsive to the detection of each idle time slot for modifying the generated address word to designate the next successive one of the time slots on the predetermined line.

Claim 11

In a time-division switch, a supervisory signaling circuit in accordance with claim 7 wherein the modifying means is reset in response to the generation of a final one of the time slots on the time-division line.

Claim 12

In a time-division switch, a supervisory signaling circuit in accordance with claim 7 wherein the modifying means is enabled in response to the storage of a message byte and the initiation of a frame of the predetermined line.