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US3703719A
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Sequence matrix
Assignee: United States Department of the Navy
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Filing: 1967-05-31
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Granted: 1972-11-21
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Expires: 1987-05-31
Abstract
Abstract A sequence matrix for decoding n binary events each having m different states without the need for a clock or a data message preamble. Sequential binary input signals are applied to an input decoder which provides steering signals to a sequence register for storing the sequential information to provide a parallel pure binary word readout. The steering signals are shifted from one storage element in the shift register to another by shift pulses generated from the sequential input signals. A timing circuit triggered by the shift pulses initiates a time gate during which the sequential input signals must be processed or the register will be reset without providing a readout. The decoder readout from the sequence register is displayed on a decoder display.
Inventors
- 👤 Henry R Beyer
- 👤 Thomas F Long
- 👤 Richard G Desipio
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 03:39
CPC Classifications
H; H04; H04L; H04L17/00; H04L17/16; H04L17/30; H03; H03M; H03M7/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
174 words
A matrix for decoding a sequential binary word defined by n input signals each having m different binary states wherein n and m are integers and the number of possible decoded combinations, M, is defined by M nm, said matrix comprising: first means to generate shift pulses in response to said binary word; an input decoder adapted to receive said binary word and provide steering signals in response thereto; m storage registers each connected to receive said shift pulses and having n storage elements for storing said signals, said registers providing a decoded parallel binary word readout; second means to provide a clearing signal applied to said registers after a predetermined time from the start of the binary word; third means to inhibit said first means from generating said shift pulses after said binary word is stored in said registers; fourth means to display said decoded parallel binary word readout; and fifth means to inhibit said first means from generating said shift pulses unless said steering signals are greater than a predetermined pulse width.
Claim 2
Dependent Claim
174 words
A matrix for decoding a sequential binary word defined by n input signals each having m different binary states wherein n and m are integers and the number of possible decoded combinations, M, is defined by M nm, said matrix comprising: first means to generate shift pulses in response to said binary word; an input decoder adapted to receive said binary word and provide steering signals in response thereto; m storage registers each connected to receive said shift pulses and having n storage elements for storing said signals, said registers providing a decoded parallel binary word readout; second means to provide a clearing signal applied to said registers after a predetermined time from the start of the binary word; third means to inhibit said first means from generating said shift pulses after said binary word is stored in said registers; fourth means to display said decoded parallel binary word readout; and fifth means to inhibit said first means from generating said shift pulses unless said steering signals are greater than a predetermined pulse width.
Claim 3
Dependent Claim
174 words
A matrix for decoding a sequential binary word defined by n input signals each having m different binary states wherein n and m are integers and the number of possible decoded combinations, M, is defined by M nm, said matrix comprising: first means to generate shift pulses in response to said binary word; an input decoder adapted to receive said binary word and provide steering signals in response thereto; m storage registers each connected to receive said shift pulses and having n storage elements for storing said signals, said registers providing a decoded parallel binary word readout; second means to provide a clearing signal applied to said registers after a predetermined time from the start of the binary word; third means to inhibit said first means from generating said shift pulses after said binary word is stored in said registers; fourth means to display said decoded parallel binary word readout; and fifth means to inhibit said first means from generating said shift pulses unless said steering signals are greater than a predetermined pulse width.
Claim 4
Dependent Claim
174 words
A matrix for decoding a sequential binary word defined by n input signals each having m different binary states wherein n and m are integers and the number of possible decoded combinations, M, is defined by M nm, said matrix comprising: first means to generate shift pulses in response to said binary word; an input decoder adapted to receive said binary word and provide steering signals in response thereto; m storage registers each connected to receive said shift pulses and having n storage elements for storing said signals, said registers providing a decoded parallel binary word readout; second means to provide a clearing signal applied to said registers after a predetermined time from the start of the binary word; third means to inhibit said first means from generating said shift pulses after said binary word is stored in said registers; fourth means to display said decoded parallel binary word readout; and fifth means to inhibit said first means from generating said shift pulses unless said steering signals are greater than a predetermined pulse width.
Claim 5
Dependent Claim
128 words
A matrix for decoding a sequential binary word defined by n input signal each having m different binary states wherein n and m are integers, said matrix comprising: input means adapted to receive said binary word to provide steering signals; generator means to generate shift pulses in response to said steering signals; register means to receive said steering signals and said shift pulses to provide a decoded parallel binary word readout; timing means responsive to said shift pulses for issuing a clearing signal for recycling said resister means after a predetermined time from the start of said binary word; and gating means responsive to said register means to inhibit said generator means from generating said shift pulses unless said steering signals are greater than a predetermined pulse width.
Claim 6
Dependent Claim
128 words
A matrix for decoding a sequential binary word defined by n input signal each having m different binary states wherein n and m are integers, said matrix comprising: input means adapted to receive said binary word to provide steering signals; generator means to generate shift pulses in response to said steering signals; register means to receive said steering signals and said shift pulses to provide a decoded parallel binary word readout; timing means responsive to said shift pulses for issuing a clearing signal for recycling said resister means after a predetermined time from the start of said binary word; and gating means responsive to said register means to inhibit said generator means from generating said shift pulses unless said steering signals are greater than a predetermined pulse width.
Claim 7
Dependent Claim
25 words
A matrix as recited in claim 2 wherein said register means comprises: m storage registers each having n storage elements for storing said steering signals.
Claim 8
Dependent Claim
22 words
A matrix as recited in claim 3 further comprising: display means responsive to said register means for displaying said parallel binary word.
Claim 9
Dependent Claim
103 words
A matrix for decoding a sequential binary word defined by n input signals each having m different binary states wherein n and m are integers, said matrix comprising: an input decoder for receiving the input signals of the binary word and providing in response thereto equivalent steering signals unless more than one input signal of the binary word are simultaneously received thereby; generator means connected to receive said steering signals for generating a shift pulse in response to each said steering signal received; and means connected to receive said steering pulses and said shift pulses to provide a decoded parallel binary word readout.
Claim 10
Dependent Claim
103 words
A matrix for decoding a sequential binary word defined by n input signals each having m different binary states wherein n and m are integers, said matrix comprising: an input decoder for receiving the input signals of the binary word and providing in response thereto equivalent steering signals unless more than one input signal of the binary word are simultaneously received thereby; generator means connected to receive said steering signals for generating a shift pulse in response to each said steering signal received; and means connected to receive said steering pulses and said shift pulses to provide a decoded parallel binary word readout.
References Cited (Backward Citations)
US3172097A
Cited
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-11-21 | 1976-05-22 | 1976-11-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-11-21 | 1980-05-22 | 1980-11-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-11-21 | 1984-05-22 | 1984-11-21 | $7700.00 | Window Closed / Lapsed |