Fet decode circuit

Claim 2

A load accessing means comprising: A. a plurality of load terminals, B. a load driver circuit, and C. a plurality of parallel decode circuits each serially connected to said load driver circuit and having: 1. an input field effect transistor with a gate and two current flow electrodes, 2. a capacitor connected across the gate and one of the current flow electrodes, the presence of a charge on said capacitor allowing current to pass through said input field effect transistor from one of said two current flow electrodes to the other of said electrodes, 3. a controllable switch for completing a discharge path parallel to said capacitor, said switch having two terminals, each of the terminals being connected to one of the electrodes of said capacitor, and 4. means controlling said switch to cause completion of the discharge path, each of said decode circuits having the current flow electrodes of its input field effect transistor connected between said load driver circuit and one of said load terminals, said means controlling said controllable switch for completing a discharge path of each decode circuit connected to a plurality of address lines for one of said load terminals, an output of each decode circuit connected to one of said load terminals.

Claim 3

A load accessing means as in claim 1 wherein said capacitor of each said decode circuit is connected across the gate and source of said input field effect transistor.

Claim 4

a capacitor connected across the gate and one of the current flow electrodes, the presence of a charge on said capacitor allowing current to pass through said input field effect transistor from one of said two current flow electrodes to the other of said electrodes,

Claim 5

a capacitor connected across the gate and one of the current flow electrodes, the presence of a charge on said capacitor allowing current to pass through said input field effect transistor from one of said two current flow electrodes to the other of said electrodes,

Claim 6

a capacitor connected across the gate and one of tHe current flow electrodes, the presence of a charge on said capacitor allowing current to pass through said input field effect transistor,

Claim 7

a capacitor connected across the gate and one of tHe current flow electrodes, the presence of a charge on said capacitor allowing current to pass through said input field effect transistor,

Claim 8

a discharge field effect transistor having its current flow electrodes each connected to one of the electrodes of said capacitor for selectively forming a discharge path internal to the decode circuit, thereby discharging said capacitor, and

Claim 9

a discharge field effect transistor having its current flow electrodes each connected to one of the electrodes of said capacitor for selectively forming a discharge path internal to the decode circuit, thereby discharging said capacitor, and

Claim 10

A load accessing means as in claim 2 wherein said controllable switch of each said decode circuit is a discharge field effect transistor having its current flow electrodes each connected to one of the electrodes of said capacitor.

Claim 11

a controllable switch for completing a discharge path parallel to said capacitor, said switch having two terminals, each of the terminals being connected to one of the electrodes of said capacitor, and

Claim 12

a controllable switch for completing a discharge path parallel to said capacitor, said switch having two terminals, each of the terminals being connected to one of the electrodes of said capacitor, and

Claim 13

means controlling said switch to cause completion of the discharge path, each of said decode circuits having the current flow electrodes of its input field effect transistor connected between said load driver circuit and one of said load terminals, said means controlling said controllable switch for completing a discharge path of each decode circuit connected to a plurality of address lines for one of said load terminals, an output of each decode circuit connected to one of said load terminals.

Claim 14

means controlling said switch to cause completion of the discharge path, each of said decode circuits having the current flow electrodes of its input field effect transistor connected between said load driver circuit and one of said load terminals, said means controlling said controllable switch for completing a discharge path of each decode circuit connected to a plurality of address lines for one of said load terminals, an output of each decode circuit connected to one of said load terminals.

Claim 15

A load accessing means as in claim 3 wherein said means of each said decode circuit controlling said discharge field effect transistor is a plurality of parallel field effect transistors connected between a voltage source and the gate of said discharge field effect transistor, the gate of each said plurality of parallel field effect transistors being adapted for connection to a memory address line.

Claim 16

a plurality of parallel field effect transistors connected between a voltage source and the gate of said discharge field effect transistor for selectively controlling said discharge field effect transistor to cause completion of the discharge path, the gate of each of said plurality of parallel field effect transistors being adapted for connection to a memory address line.

Claim 17

a plurality of parallel field effect transistors connected between a voltage source and the gate of said discharge field effect transistor for selectively controlling said discharge field effect transistor to cause completion of the discharge path, the gate of each of said plurality of parallel field effect transistors being adapted for connection to a memory address line.

Claim 18

A load accessing means as in claim 1, each said decode circuit additionally comprising: E. means for applying a charge to said capacitor.

Claim 19

A load accessing means as in claim 5 wherein said means in each said decode circuit for applying the charge to said capacitor is a restore field effect transistor serially connected between said capacitor and a source of voltage and having a control pulse source coupled to its gate.

Claim 20

A load accessing means as in claim 6 wherein said controllable switch of each said decode circuit is a discharge field effect transistor having its current flow electrodes each connEcted to one of the electrodes of said capacitor, and said means controlling said switch is a plurality of parallel field effect transistors connected between a voltage source and the gate of said discharge field effect transistor, the gate of each of said plurality of parallel field effect transistors connected to a memory address line.

Claim 21

A load accessing means as in claim 1 wherein said load is a memory and said load driver circuit includes at least one bipolar transistor connected to a current flow electrode of said input field effect transistor.

Claim 22

A decode circuit having: A. an input field effect transistor with a gate and two current flow electrodes, B. a capacitor connected across the gate and one of the current flow electrodes, the presence of a charge on said capacitor allowing current to pass through said input field effect transistor, C. means for completing a discharge path parallel to said capacitor comprising a discharge field effect transistor having its current flow electrodes each connected to one of the electrodes of said bootstrap capacitor, D. means controlling said means for completing a discharge path to cause completion of the discharge path comprising a plurality of parallel field effect transistors connected between a voltage source and the gate of said discharge field effect transistor, the gate of each of said plurality of parallel field effect transistors being connected to a memory address line, E. means for applying a charge to said bootstrap capacitor comprising a restore field effect transistor serially connected between said bootstrap capacitor and a source of voltage and having a control pulse source coupled to its gate, and F. an isolation field effect transistor serially connected between a reference potential insufficient to turn on said discharge field effect transistor and a current flow electrode of each of said parallel field effect transistors, and a control pulse source coupled to the gate of said isolation field effect transistor.

Claim 23

A decode circuit having: A. an input field effect transistor with a gate and two current flow electrodes, B. a capacitor connected across the gate and one of the current flow electrodes, the presence of a charge on said capacitor allowing current to pass through said input field effect transistor, C. means for completing a discharge path parallel to said capacitor comprising a discharge field effect transistor having its current flow electrodes each connected to one of the electrodes of said bootstrap capacitor, D. means controlling said means for completing a discharge path to cause completion of the discharge path comprising a plurality of parallel field effect transistors connected between a voltage source and the gate of said discharge field effect transistor, the gate of each of said plurality of parallel field effect transistors being connected to a memory address line, E. means for applying a charge to said bootstrap capacitor comprising a restore field effect transistor serially connected between said bootstrap capacitor and a source of voltage and having a control pulse source coupled to its gate, and F. an isolation field effect transistor serially connected between a reference potential insufficient to turn on said discharge field effect transistor and a current flow electrode of each of said parallel field effect transistors, and a control pulse source coupled to the gate of said isolation field effect transistor.

Claim 24

A decode circuit as in claim 9 in which said source of voltage connected to said restore field effect transistor and said voltage source connected to said plurality of parallel field effect transistors are common.

Claim 25

A decode circuit as in claim 9 in which said control pulse source coupled to the gate of said restore field effect transistor and said control pulse source coupled to the gate of said isolation field effect transistor are common.

Claim 26

A decode circuit as in claim 9 additionally comprising a second discharge field effect transistor connected between a current flow electrode of said input field effect transistor and a reference potential for discharging an inherent capacitance across said current flow electrode and the reference potential, and a means controlling said second discharge field effect transistor.

Claim 27

A decode circuit as in claim 12 wherein said means controlling said second discharge field effect transistor and said means controlling said discharge field effect transistor are common.

Claim 28

A decode circuit as in claim 9 additionally comprising a second isolation field effect transistor serially connected between said second discharge field effect transistor and said reference potential, whereby the application of a multiplexed signal to the gate of said discharge field effect transistor is insufficient to turn on said discharge field effect transistor in the absence of a control pulse applied to the gate of said second isolation field effect transistor.

Claim 29

A memory accessing means comprising: A. a memory driver circuit, and B. a plurality of parallel decode circuits each connected serially to said memory driver circuit, each decode circuit having:

Claim 30

A memory accessing means comprising: A. a memory driver circuit, and B. a plurality of parallel decode circuits each connected serially to said memory driver circuit, each decode circuit having: