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US3702394A Expired / Lapsed US ⏱️ 0.0 years remaining

Electronic double integrator

Assignee: United States Department of the Navy
•
Filing: 1970-09-17
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Granted: 1972-11-07
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Expires: 1990-09-17
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Abstract

Abstract An electronic double integrator circuit including an accelerometer; first and second integrators, at least one of which has an operational amplifier with capacitive-resistive feedback; and a logic circuit. The system provides an output when the accumulated input derived from the accelerometer indicates that a spatial, rather than time, interval has occurred.

Inventors

  • 👤 Paul J Rainsberger
  • 👤 Charles M Dye Jr

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 23:07
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/18; G06G7/184; G06G7/186; G06G7/1865; G06G7/48; G06G7/78

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 257 words
An electronic double integrator system for providing an output signal a predetermined spatial interval after initiation comprising: means for providing an electrical signal in response to spatial acceleration experienced by said system; first integrating means coupled to said signal providing means for integrating said signal and providing an output in response to said integrated signal, including an operational amplifier, having capacitive feedback, coupled to said signal providing means and a transistor having its first terminal coupled to the output of said operational amplifier wherein said first terminal is its base terminal, its second terminal coupled to a current source, and its third terminal coupled to a second integrating means, wherein said third terminal provides said output of said first integrating means, such that the output of said transistor is proportional to the output of said operational amplifier; second integrating means coupled to said first integrating means for integrating said transistor output and providing said integrated transistor output as an output, including an E-cell having a first terminal coupled to said third terminal of the transistor and a second terminal coupled to the system common ground; and means coupled to said second integrating means and gated by a predetermined value of said integrating means output for providing said system output, including a silicon controlled rectifier having its gate terminal coupled to said first terminal of said E-cell, its anode terminal coupled to a source of electrical energy, and its cathode terminal coupled to the system output terminals; wherein said predetermined value is representative of said predetermined spatial interval.
Claim 2
Dependent Claim 257 words
An electronic double integrator system for providing an output signal a predetermined spatial interval after initiation comprising: means for providing an electrical signal in response to spatial acceleration experienced by said system; first integrating means coupled to said signal providing means for integrating said signal and providing an output in response to said integrated signal, including an operational amplifier, having capacitive feedback, coupled to said signal providing means and a transistor having its first terminal coupled to the output of said operational amplifier wherein said first terminal is its base terminal, its second terminal coupled to a current source, and its third terminal coupled to a second integrating means, wherein said third terminal provides said output of said first integrating means, such that the output of said transistor is proportional to the output of said operational amplifier; second integrating means coupled to said first integrating means for integrating said transistor output and providing said integrated transistor output as an output, including an E-cell having a first terminal coupled to said third terminal of the transistor and a second terminal coupled to the system common ground; and means coupled to said second integrating means and gated by a predetermined value of said integrating means output for providing said system output, including a silicon controlled rectifier having its gate terminal coupled to said first terminal of said E-cell, its anode terminal coupled to a source of electrical energy, and its cathode terminal coupled to the system output terminals; wherein said predetermined value is representative of said predetermined spatial interval.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-11-07 1976-05-08 1976-11-07 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-11-07 1980-05-08 1980-11-07 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-11-07 1984-05-08 1984-11-07 $7700.00 Window Closed / Lapsed

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