Patent US3701198A successfully refreshed from Google Patents.
US3701198A
Expired / Lapsed
US
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Monolithic integrated circuit structures and methods of making same
Assignee: AT&T Inc
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Filing: 1970-08-14
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Granted: 1972-10-31
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Expires: 1990-08-14
Abstract
Abstract An annular PN junction in conjunction with a relatively high resistivity substrate enables improved means for isolating functional elements in a monolithic semiconductor integrated circuit. In a semiconductor wafer, localized emitter zones and collector zones extend to a common depth from the surface of the wafer. The collector zone is annular in shape and encloses laterally the emitter zone. The resistivities and spacings of the regions in the wafer are such that with the annular PN junction reverse-biased, the depletion region therefrom extends completely underneath the material enclosed by the annular zone and thereby provides electrical isolation for a functional element in the enclosed material.
Inventors
- 👤 Vincent J Glinski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:25
CPC Classifications
H; H10; H10D; H10D99/00; H10W; H10W10/00; H10W10/01; H10W10/051; H10W10/50
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
175 words
A method of fabricating a monolithic semiconductor integrated circuit comprising the steps of forming a relatively thin, relatively low resistivity layer of a first type semiconductivity contiguous with a surface of a monocrystalline, relatively high resistivity body of the first type semiconductivity, forming simultaneously a pattern of localized zones of a second type semiconductivity completely through the layer, each of said zones forming a PN junction with the layer, and forming electrode connections to the zones and to the layer, wherein the pattern of zones includes an annular-like zone which encloses a portion of the layer, the relative spacings and doping levels of the zones, of the layer, and of the body beiNg such that with the junction between the annular-like zone and the layer reverse-biased by some amount less than avalanche, the depletion region from that junction extends completely underneath all of that part of the layer enclosed by the annular-like zone, whereby that portion of the layer enclosed by the annular-like zone is electrically isolated from the remaining portions of first type semiconductivity.
Claim 2
Independent Claim
175 words
A method of fabricating a monolithic semiconductor integrated circuit comprising the steps of forming a relatively thin, relatively low resistivity layer of a first type semiconductivity contiguous with a surface of a monocrystalline, relatively high resistivity body of the first type semiconductivity, forming simultaneously a pattern of localized zones of a second type semiconductivity completely through the layer, each of said zones forming a PN junction with the layer, and forming electrode connections to the zones and to the layer, wherein the pattern of zones includes an annular-like zone which encloses a portion of the layer, the relative spacings and doping levels of the zones, of the layer, and of the body beiNg such that with the junction between the annular-like zone and the layer reverse-biased by some amount less than avalanche, the depletion region from that junction extends completely underneath all of that part of the layer enclosed by the annular-like zone, whereby that portion of the layer enclosed by the annular-like zone is electrically isolated from the remaining portions of first type semiconductivity.
Claim 3
Independent Claim
256 words
A method of fabricating a self-isolated bipolar transistor in a monolithic semiconductor integrated circuit comprising the steps of forming a first pattern of localized zones including a pair of spaced zones of first type semiconductivity adjacent a surface of a bulk portion of second type semiconductivity of relatively high resistivity, forming a relatively thin, relatively low resistivity layer of second type semiconductivity overlying the surface of the bulk portion and the first pattern of zones, forming simultaneously by a selective introduction of impurities into the surface of the layer a second pattern of localized zones including an annular-like zone and an emitter zone within and spaced from the annular-like zone, the zones of the second pattern being of the first type semiconductivity, and all of said zones of the second pattern forming a PN junction with the layer, and all of said zones of the second pattern extending completely through the layer to a common depth from the surface of the layer, and forming electrode connections to the second pattern of zones and to the layer, wherein the selective zone forming step is controlled such that the emitter zone is smaller than the space between the pair of zones of the first pattern and is registered with and formed between said pair of zones, and the annular-like zone is formed such that it intersects both of the pair of zones, whereby the space between the pair of zones can be depleted of free charge carriers, thus to provide electrical isolation for the semiconductive material contained therewithin.
Claim 4
Independent Claim
256 words
A method of fabricating a self-isolated bipolar transistor in a monolithic semiconductor integrated circuit comprising the steps of forming a first pattern of localized zones including a pair of spaced zones of first type semiconductivity adjacent a surface of a bulk portion of second type semiconductivity of relatively high resistivity, forming a relatively thin, relatively low resistivity layer of second type semiconductivity overlying the surface of the bulk portion and the first pattern of zones, forming simultaneously by a selective introduction of impurities into the surface of the layer a second pattern of localized zones including an annular-like zone and an emitter zone within and spaced from the annular-like zone, the zones of the second pattern being of the first type semiconductivity, and all of said zones of the second pattern forming a PN junction with the layer, and all of said zones of the second pattern extending completely through the layer to a common depth from the surface of the layer, and forming electrode connections to the second pattern of zones and to the layer, wherein the selective zone forming step is controlled such that the emitter zone is smaller than the space between the pair of zones of the first pattern and is registered with and formed between said pair of zones, and the annular-like zone is formed such that it intersects both of the pair of zones, whereby the space between the pair of zones can be depleted of free charge carriers, thus to provide electrical isolation for the semiconductive material contained therewithin.
Claim 5
Dependent Claim
219 words
A process for forming an integrated circuit having a plurality of functional elements isolated one from another and which requires only three masking operations and one selective impurity-introducing step up to and including the step which defines the first layer of electrode metallization which comprises the steps of: forming a relatively thin, relatively low resistivity layer of a first type semiconductivity contiguous with a surface of a monocrystalline, relatively high resistivity bulk portion of the first type semiconductivity; forming simultaneously by the one selective introduction of impurities a pattern of localized zones including annular-like zones of a second type semiconductivity all extending completely through the layer to a common depth, and such that each of said zones forms a PN junction with the layer; forming electrode connections to the zones and to the layer; and controlling the above-recited steps so that the relative spacings and doping levels of the zones, of the layer, and of the bulk portion are such that with the junction between an annular-like zone and the layer reverse-biased by some amount less than avalanche, the depletion region from that junction extends completely underneath that part of the layer enclosed by the annular-like zone, whereby that portion of the layer enclosed by the annular-like zone is electrically isolated from the remaining portions of first type semiconductivity.
Claim 6
Dependent Claim
219 words
A process for forming an integrated circuit having a plurality of functional elements isolated one from another and which requires only three masking operations and one selective impurity-introducing step up to and including the step which defines the first layer of electrode metallization which comprises the steps of: forming a relatively thin, relatively low resistivity layer of a first type semiconductivity contiguous with a surface of a monocrystalline, relatively high resistivity bulk portion of the first type semiconductivity; forming simultaneously by the one selective introduction of impurities a pattern of localized zones including annular-like zones of a second type semiconductivity all extending completely through the layer to a common depth, and such that each of said zones forms a PN junction with the layer; forming electrode connections to the zones and to the layer; and controlling the above-recited steps so that the relative spacings and doping levels of the zones, of the layer, and of the bulk portion are such that with the junction between an annular-like zone and the layer reverse-biased by some amount less than avalanche, the depletion region from that junction extends completely underneath that part of the layer enclosed by the annular-like zone, whereby that portion of the layer enclosed by the annular-like zone is electrically isolated from the remaining portions of first type semiconductivity.
Claim 7
Dependent Claim
30 words
A method as recited in claim 3 wherein the layer is formed by nonselective introduction of impurities of the first type semiconductivity into the entire surface of the monocrystalline body.
Claim 8
Dependent Claim
18 words
A method as recited in claim 4 wherein the nonselective introduction of impurities is accomplished by ion implantation.
Claim 9
Dependent Claim
19 words
A method as recited in claim 4 wherein the nonselective introduction of impurities is accomplished by solid state diffusion.
Claim 10
Dependent Claim
22 words
A method as recited in claim 3 wherein the layer is formed by epitaxial dePosition upon the surface of the monocrystalline body.
Claim 11
Dependent Claim
22 words
A method as recited in claim 3 wherein the resistivity of the body is in the range of 10 to 2,500 ohm-centimeters.
Claim 12
Dependent Claim
17 words
A method as recited in claim 3 wherein the resistivity of the layer is about 0.1 ohm-centimeters.
Claim 13
Dependent Claim
33 words
A method as recited in claim 9 wherein the resistivity of the body is at least 100 ohm-centimeters and the minimum inner diameter of the annular-like zone is less than about 10 microns.
Claim 14
Dependent Claim
47 words
A method as recited in claim 3 wherein one of the zones of the second type conductivity is formed simultaneously with and laterally within and so as to be enclosed by but not intersected by the annular-like zone, said zone for providing an emitter for a transistor.
Claim 15
Dependent Claim
80 words
A method as recited in claim 11 wherein: one of the electrodes contacts the annular-like zone for providing ohmic connection to the collector of a transistor; a second one of the electrodes contacts the emitter zone of second type semiconductivity zone for providing low resistivity electrical connection to the emitter of the transistor; and a third electrode is formed laterally between and spaced from the emitter and collector electrodes for providing low resistance connection to the base of the transistor.
Claim 16
Dependent Claim
74 words
A method as recited in claim 12 comprising the additional step of forming a buried localized zone of second type semiconductivity underlying the layer and disposed so as to intersect a portion of the annular-like zone and so as to extend from the annular-like zone underneath the base electrode to an extent insufficient to intersect the emitter zone so as thereby to reduce the voltage required to produce sufficient depletion that isolation is achieved.
Claim 17
Independent Claim
271 words
A method for forming an integrated circuit having a plurality of bipolar transistors isolated one from another and which method requires only three masking operations and one selective impurity-introducing step up to and including the step which defines the first layer of electrode metallization comprising the steps of: forming a semiconductor body including a relatively thin, relatively low resistivity layer of a first type semiconductivity contiguous with a surface of a monocrystalline, relatively high resistivity bulk portion of the first type semiconductivity; forming over the surface of the layer a first mask having a plurality of annular-like apertures; selectively introducing impurities through the apertures in the mask to form a pattern of annular-like localized zones extending completely through the layer to a common depth, and such that the zones form PN junctions with the layer; forming over the surface of the layer and zones a second mask having apertures where it is desired to contact selectively portions of the layer and zones; depositing conductive material over and through the apertures in the second mask; forming a third mask over the conductive layer such that the pattern in the second mask defines the desired electrode configuration; removing the portions of the conductive material not protected by the third mask; and controlling the above-recited steps so that the relative spacings and doping levels of the zones, of the layer, and of the bulk portion are such that with the junction between the annular-like zone and the layer reverse-biased by some amount less than avalanche, the depletion region from that junction extends completely underneath that part of the layer enclosed by the annular-like zone.
Claim 18
Independent Claim
271 words
A method for forming an integrated circuit having a plurality of bipolar transistors isolated one from another and which method requires only three masking operations and one selective impurity-introducing step up to and including the step which defines the first layer of electrode metallization comprising the steps of: forming a semiconductor body including a relatively thin, relatively low resistivity layer of a first type semiconductivity contiguous with a surface of a monocrystalline, relatively high resistivity bulk portion of the first type semiconductivity; forming over the surface of the layer a first mask having a plurality of annular-like apertures; selectively introducing impurities through the apertures in the mask to form a pattern of annular-like localized zones extending completely through the layer to a common depth, and such that the zones form PN junctions with the layer; forming over the surface of the layer and zones a second mask having apertures where it is desired to contact selectively portions of the layer and zones; depositing conductive material over and through the apertures in the second mask; forming a third mask over the conductive layer such that the pattern in the second mask defines the desired electrode configuration; removing the portions of the conductive material not protected by the third mask; and controlling the above-recited steps so that the relative spacings and doping levels of the zones, of the layer, and of the bulk portion are such that with the junction between the annular-like zone and the layer reverse-biased by some amount less than avalanche, the depletion region from that junction extends completely underneath that part of the layer enclosed by the annular-like zone.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-31 | 1976-05-01 | 1976-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-31 | 1980-05-01 | 1980-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-31 | 1984-05-01 | 1984-10-31 | $7700.00 | Window Closed / Lapsed |