US3701123A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hybrid integrated circuit module
Assignee: HP Inc
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Filing: 1969-10-29
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Granted: 1972-10-24
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Expires: 1989-10-29
Abstract
Abstract A visual display module includes a thin thermally conductive substrate. The substrate has a narrow top edge surface on which a linear array of closely spaced electroluminescent display elements are mounted, a bottom edge surface along which there are disposed terminals for receiving input power and binary coded signals for controlling the display elements, and a lateral surface on which an integrated circuit chip and a signal conductors are located. The integrated circuit chip contains a decoding network for selectively addressing the display elements in response to the binary coded signals, write-erase gating means for conditioning an addressed display element into an ''''on'''' or ''''off'''' state, and memory circuits for holding each display element in its ''''selected'''' state. The display elements are disposed in a viewing plane perpendicular to the lateral surface of the substrate, so that a plurality of modules can be stacked adjacent to one another to produce an expandable high density display field.
Inventors
- 👤 John C Barrett
- 👤 Howard C Borden
- 👤 Egon E Loebner
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:51
CPC Classifications
H; H03; H03K; H03K21/00; H03K21/08; G; G09; G09G; G09G3/00; G09G3/20; G09G3/22; G09G3/30; G09G3/32
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
252 words
A conditionable bistable memory circuit responsive to two signals for driving a light emitting diode from a potential source, said memory circuit comprising: first and second bipolar transistors of complimentary conductivity types and each having two main current carrying electrodes and a control electrode; the control electrode of each transistor being coupled to one main current carrying electrode of the other transistor; the other main current carrying electrode of the first transistor being coupled to said potential source, and the other main current-carrying electrode of the second transistor being coupled to said light emitting diode; a single control input coupled only to the control electrode of one of said first and second transistors; third and fourth transistors each having a pair of main current carrying electrodes and a control electrode; said main current carrying electrodes of said third and fourth transistors being coupled in series to said single control input; said third and fourth transistors both being of the same conductivity type as said one of the first and second transistors to which said single control input is coupled; the control electrode of one of said third and fourth transistors being coupled to one of said two input signals; and the control electrode of the other of said third and fourth transistors being coupled to the other of said two input signals; whereby said one input signal operates to condition said first and second transistors to be latched in either a conducting or non-conducting mode in response to said other input signal.
Claim 2
Dependent Claim
252 words
A conditionable bistable memory circuit responsive to two signals for driving a light emitting diode from a potential source, said memory circuit comprising: first and second bipolar transistors of complimentary conductivity types and each having two main current carrying electrodes and a control electrode; the control electrode of each transistor being coupled to one main current carrying electrode of the other transistor; the other main current carrying electrode of the first transistor being coupled to said potential source, and the other main current-carrying electrode of the second transistor being coupled to said light emitting diode; a single control input coupled only to the control electrode of one of said first and second transistors; third and fourth transistors each having a pair of main current carrying electrodes and a control electrode; said main current carrying electrodes of said third and fourth transistors being coupled in series to said single control input; said third and fourth transistors both being of the same conductivity type as said one of the first and second transistors to which said single control input is coupled; the control electrode of one of said third and fourth transistors being coupled to one of said two input signals; and the control electrode of the other of said third and fourth transistors being coupled to the other of said two input signals; whereby said one input signal operates to condition said first and second transistors to be latched in either a conducting or non-conducting mode in response to said other input signal.
Claim 3
Dependent Claim
53 words
The circuit of claim 1, further including resistance means coupled between the control electrode of said second transistor and the main current carrying electrode of said second transistor which is coupled to said load, said resistance means being operable to set the threshold level between conducting and non-conducting modes of the memory circuit.
Claim 4
Dependent Claim
141 words
A hybrid integrated circuit module comprising: a substrate having a plurality of planar surfaces; a plurality of indicating elements disposed solely on a first one of said surfaces of said substrate; a plurality of signal receiving terminals disposed solely along a second surface of said substrate which is opposite to said first surface, the number of said signal receiving terminals being less than the number of said indicating elements; signal translating integrated network means mounted on said substrate inteRmediate said first and second opposite lateral surfaces for selectively energizing and de-energizing each one of said plurality of indicating elements in response to coded signals applied to said plurality of signal receiving terminals; and conductor means disposed on said substrate for electrically coupling said plurality of indicating elements and said plurality of signal receiving terminals to said signal translating integrated network means.
Claim 5
Dependent Claim
141 words
A hybrid integrated circuit module comprising: a substrate having a plurality of planar surfaces; a plurality of indicating elements disposed solely on a first one of said surfaces of said substrate; a plurality of signal receiving terminals disposed solely along a second surface of said substrate which is opposite to said first surface, the number of said signal receiving terminals being less than the number of said indicating elements; signal translating integrated network means mounted on said substrate inteRmediate said first and second opposite lateral surfaces for selectively energizing and de-energizing each one of said plurality of indicating elements in response to coded signals applied to said plurality of signal receiving terminals; and conductor means disposed on said substrate for electrically coupling said plurality of indicating elements and said plurality of signal receiving terminals to said signal translating integrated network means.
Claim 6
Dependent Claim
122 words
The module of claim 3, said substrate including an electrically and thermally conductive sheet wherein said first and second opposite surfaces are edges of said sheet in parallel planes, and an electrically insulating film overlaying a lateral surface of said sheet intermediate said first and second edges; said conductor means being a conductor pattern overlaying said insulating film and including said signal receiving terminals and also including contact points coupled to said indicating elements and said signal translating integrated network means said signal receiving terminals being disposed to extend beyond said second edge surface; and said signal translating integrated network means being a monolithic integrated circuit chip having contact points coupled to selected ones of said contact points of said conductor pattern.
Claim 7
Dependent Claim
145 words
The module of claim 3, wherein said signal translating integrated network means includes: decoding means having a plurality of inputs for receiving binary signals applied to said plurality of signal receiving terminals, and a plurality of outputs providing addressing signals corresponding respectively to said plurality of indicating elements; a plurality of means for respectively coupling each output of said decoding means to the corresponding one of said indicating elements, each of said coupling means including: first means for gating the addressing signals from an output of said decoding means, said first gating means having an enabling input; memory means responsive to the addressing signals gated by said first gating means for holding the corresponding one of said indicating elements in an energized or de-energized state; and means for coupling the enabling inputs of said first gating means in common for receiving a module enabling signal.
Claim 8
Dependent Claim
82 words
The module of claim 5, wherein each of said plurality of coupling means further includes second gating means coupled between said first gating means and said memory means, said gating means having a write-erase control input for conditioning said memory means to energize or de-energize said indicating element in synchronism with the output from said first gating means, and wherein said signal translating integrated network means further includes means for coupling said write-erase control inputs in common for receiving a write-erase signal.
Claim 9
Dependent Claim
224 words
The module of claim 6, said memory means including a bistable latch circuit including: first and second bipolar transistors of complementary conductivity types and each having base, emitter and collector electrodes; the base electrode of each transistor being coupled to the collector electrode of the other transistor; the emitter electrode of the first transistor being connectable to a potential source, and the emitter electrode of the second transistor being coupled to the corresponding one of said indicating elements; and a single control input coupled only to the base electrode of one of said first and second transistors for conditioning both of said transistors in either a conducting or a non-conducting mode; said second gating means including: third and fourth transistors of like conductivity types and each having a pair of main current carrying electrodes and a control electrode; the main current carrying electrodes of said third and fourth transistors being coupled in series to said single control input; the control electrode of one of said third and fourth transistors being coupled to the output of said first gating meanS, and the control electrode of the other of said third and fourth transistors being coupled to said write-erase control input to energize or de-energize indicating elements addressed by said decoding means in response to said write-erase signal and in synchronism with said module enabling signal.
Claim 10
Dependent Claim
19 words
The module of claim 7, wherein each of said plurality of indicating elements is a semiconductor light emitting diode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-24 | 1976-04-24 | 1976-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-24 | 1980-04-24 | 1980-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-24 | 1984-04-24 | 1984-10-24 | $7700.00 | Window Closed / Lapsed |