Control circuitry and voltage source for use with charge storage diode

Claim 2

Control circuit apparatus for extremely rapidly causing minority carriers to be produced in a first charge storage diode which then acts as a short circuit in the reverse direction for a preselected period of time and then automAtically acts an an open circuit in the reverse direction comprising: a second diode; a third diode; the cathode of the second diode being coupled to the anode of the third diode and the cathode of the first diode; a first voltage source being coupled to the anode of the first diode; first means coupled to the anode of the second diode and second means coupled to the cathode of the third diode for causing forward conduction through the second and third diodes; and third means coupled to the anode of the second diode for inhibiting forward conduction in the second and third diodes such that minority carriers are temporarily trapped in the second diode which make the second diode appear as a short circuit that permits a flow of current from the first voltage source through the first charge storage diode in the forward direction, and through the second diode in the reverse direction into the inhibiting means, that dissipates the minority carriers in the second diode and produces minority carriers in the first charge storage diode.

Claim 3

The apparatus of claim 1 wherein: the second diode is a charge storage type diode; the third diode is a Schottky-barrier type diode; the first means comprises a second voltage source and a first resistor; one end of the first resistor being coupled to the second voltage source and the other end being coupled to the anode of the second diode; the second means comprises a third voltage source; the fourth means is a first NPN transistor; and the collector of the first transistor being coupled to the anode of the second diode.

Claim 4

The apparatus of claim 1 further comprising: a fourth diode; the cathode of the fourth diode being coupled to the cathode of the second diode.

Claim 5

The apparatus of claim 3 wherein the fourth diode is a Schottky-barrier type diode.

Claim 6

The apparatus of claim 4 wherein the first voltage source comprises: a fifth diode which is a charge storage type diode; a sixth diode which is a Schottky-barrier type diode; a second resistor; one end of the second resistor being coupled to the anode of the fifth diode and the anode of the sixth diode; a second NPN transistor; and the collector of the second transistor being coupled to the anode of the fifth diode and the anode of the sixth diode.

Claim 7

The apparatus of claim 5 wherein the cathode of the sixth diode is coupled to the anode of the first diode.

Claim 8

In combination: a semiconductor memory array of interconnected rows and columns of memory cells; each of the memory cells of a given row being coupled to a word line and each of the memory cells of a given column being coupled to a digit line; a plurality of first charge storage diodes which, when minority carriers are produced within them, act as short circuits in the reverse direction for a preselected period of time, and then automatically act as open circuits in the reverse direction; one of the plurality of first diodes being coupled to each digit line by the cathode; an information detector being coupled to the anodes of the first diodes; a first voltage source comprising: a second charge storage diode; a third Schottky-barrier diode; and a first resistor; the anode of the second charge storage diode being coupled to one end of the first resistor and the anode of the third diode; a first NPN transistor coupled by the collector to the anode of the second diode; the cathode of the second diode being coupled to the anodes of the first diodes; a plurality of control circuits equal to the number of digit lines; each of the control circuits comprising: a fourth charge storage diode; a fifth Schottky-barrier diode; the cathode of the fourth diode being coupled to the anode of the fifth diode and the cathode of the first diode; and first means coupled to the anode of the fourth diode and second means coupled to the cathOde of the fifth diode for causing forward conduction through the fourth and fifth diodes; a plurality of Schottky-barrier diodes; each of the sixth diodes being coupled to a digit line by the cathode; and third means coupled to the anode of the fourth diode for inhibiting forward conduction in the fourth and fifth diodes such that minority carriers are temporarily trapped in the fourth diode which make the fourth diode appear as a short circuit that permits a flow of current from the first voltage source through the first diode in the forward direction and through the fourth diode in the reverse direction into the inhibiting means, that dissipates the minority carriers in the fourth diode and produces minority carriers in the first charge storage diode.

Claim 9

In combination: a semiconductor memory array of interconnected rows and columns of memory cells; each of the memory cells of a given row being coupled to a word line and each of the memory cells of a given column being coupled to a digit line; a plurality of first charge storage diodes which, when minority carriers are produced within them, act as short circuits in the reverse direction for a preselected period of time, and then automatically act as open circuits in the reverse direction; one of the plurality of first diodes being coupled to each digit line by the cathode; an information detector being coupled to the anodes of the first diodes; a first voltage source comprising: a second charge storage diode; a third Schottky-barrier diode; and a first resistor; the anode of the second charge storage diode being coupled to one end of the first resistor and the anode of the third diode; a first NPN transistor coupled by the collector to the anode of the second diode; the cathode of the second diode being coupled to the anodes of the first diodes; a plurality of control circuits equal to the number of digit lines; each of the control circuits comprising: a fourth charge storage diode; a fifth Schottky-barrier diode; the cathode of the fourth diode being coupled to the anode of the fifth diode and the cathode of the first diode; and first means coupled to the anode of the fourth diode and second means coupled to the cathOde of the fifth diode for causing forward conduction through the fourth and fifth diodes; a plurality of Schottky-barrier diodes; each of the sixth diodes being coupled to a digit line by the cathode; and third means coupled to the anode of the fourth diode for inhibiting forward conduction in the fourth and fifth diodes such that minority carriers are temporarily trapped in the fourth diode which make the fourth diode appear as a short circuit that permits a flow of current from the first voltage source through the first diode in the forward direction and through the fourth diode in the reverse direction into the inhibiting means, that dissipates the minority carriers in the fourth diode and produces minority carriers in the first charge storage diode.