Abstract A logical frequency divider comprising at least one stage of division by two consisting of four logical gates A, B, C and D, the gates being connected as follows: the output from the first gate A controls an input to the second gate B; the output from the second gate B controls an input to the first gate A and an input to the third gate C; the output from the third gate C controls a second input to the first gate A, a second input to the second gate B and an input to the fourth gate D; the output from the fourth gate D controls a third input to the second gate B, a second input to the third gate C. The input signal to the stage of division by two controls a third input to the third gate C and a second input to the fourth gate D.
Inventors
👤 Eric Andre Vittoz
Bibliographic Details
Application Number—
JurisdictionUS
Data Sourcegoogle_patents
Last Synchronized2026-10-30 05:19
CPC Classifications
H; H03; H03K; H03K23/00; H03K23/58; H03K21/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
135 words
A logical frequency divider comprising at least one stage of division by two, consisting of four logical gates A, B, C and D, where the output from the first gate A controls an input to the second gate, the output from the second gate B controls an input to the first gate and an input to the third gate, the output from the third gate C controls a second input to the first gate, a second input to the second gate and an input to the fourth gate, the output from the fourth gate D controls a third input to the second gate and a second input to the third gate; and finally the input signal to the stage controls a third input to the third gate and a second input to the fourth gate.
Claim 2
Dependent Claim
135 words
A logical frequency divider comprising at least one stage of division by two, consisting of four logical gates A, B, C and D, where the output from the first gate A controls an input to the second gate, the output from the second gate B controls an input to the first gate and an input to the third gate, the output from the third gate C controls a second input to the first gate, a second input to the second gate and an input to the fourth gate, the output from the fourth gate D controls a third input to the second gate and a second input to the third gate; and finally the input signal to the stage controls a third input to the third gate and a second input to the fourth gate.
Claim 3
Dependent Claim
13 words
A divider according to the claim 1, in which the gates are NOR-gates.
Claim 4
Dependent Claim
13 words
A divider according to the claim 1, in which the gates are NAND-gates.
Claim 5
Dependent Claim
19 words
A divider according to claim 2, comprising means for increasing the switching times of the first and fourth gates.
Claim 6
Dependent Claim
17 words
A divider according to the claim 4, in which the divider is made by integrated circuit techniques.
Claim 7
Dependent Claim
19 words
A divider according to claim 3 comprising means for increasing the switching times of the first and fourth gates.