US3700915A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Full-power/half-power logic gate
Assignee: Motorola Solutions Inc
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Filing: 1971-01-18
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Granted: 1972-10-24
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Expires: 1991-01-18
Abstract
Abstract An integrated circuit logic gate suitable for use in LSI arrays provides OR and NOR logic outputs and includes additional collector and emitter resistors causing the array to be operated at half power levels. If a full power array is desired optional metalization shunting of the additional emitter and collector resistors is provided while maintaining the full logic swing across the same DC reference level which exists for half power operation. Thus, full power and half power gates may be interconnected without necessitating the use of additional interface circuits.
Inventors
- 👤 Robert R Marley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:28
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0175; H03K19/017581
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
319 words
An integrated circuit logic gate for optional operation as full power or reduced power gate including in combination: first and at least one second transistors, each of the same conductivity type and each having emitter, collector, and base electrodes, with the emitter electrodes of tHe first and second transistors being coupled together at a first junction point; first and second resistance means coupled with the collectors of the first and second transistors, respectively, and coupled together at a second junction point; first and second supply terminals adapted to receive a DC potential therebetween; third resistance means coupled between the second junction point and the first supply terminal; fourth and fifth resistance means coupled together at a third junction point and in series circuit between the second supply terminal and the first junction point; reference circuit means coupled with the base electrode of the first transistor for supplying a reference potential thereto; signal input means coupled with the base electrode of the second transistor for applying input signals thereto; the gate operating in a first state with one of the first and second transistors conductive for one predetermined relationship of the input signal and the reference potential and operating in a second state with the other of the first and second transistors conductive for a second predetermined relationship of the input signal and the reference potential; first and second conductive means connected to opposite ends of the third resistance means and adapted for physical interconnection; third and fourth conductive means connected to opposite ends of the fourth resistance means and adapted for physical interconnection, the logic gate operating as a reduced power gate in the absence of interconnection of the first and second and third and fourth conductive means and operating as a full power gate with concurrent physical interconnection of the first conductive means to the second conductive means and the third conductive means to the fourth conductive means.
Claim 2
Dependent Claim
319 words
An integrated circuit logic gate for optional operation as full power or reduced power gate including in combination: first and at least one second transistors, each of the same conductivity type and each having emitter, collector, and base electrodes, with the emitter electrodes of tHe first and second transistors being coupled together at a first junction point; first and second resistance means coupled with the collectors of the first and second transistors, respectively, and coupled together at a second junction point; first and second supply terminals adapted to receive a DC potential therebetween; third resistance means coupled between the second junction point and the first supply terminal; fourth and fifth resistance means coupled together at a third junction point and in series circuit between the second supply terminal and the first junction point; reference circuit means coupled with the base electrode of the first transistor for supplying a reference potential thereto; signal input means coupled with the base electrode of the second transistor for applying input signals thereto; the gate operating in a first state with one of the first and second transistors conductive for one predetermined relationship of the input signal and the reference potential and operating in a second state with the other of the first and second transistors conductive for a second predetermined relationship of the input signal and the reference potential; first and second conductive means connected to opposite ends of the third resistance means and adapted for physical interconnection; third and fourth conductive means connected to opposite ends of the fourth resistance means and adapted for physical interconnection, the logic gate operating as a reduced power gate in the absence of interconnection of the first and second and third and fourth conductive means and operating as a full power gate with concurrent physical interconnection of the first conductive means to the second conductive means and the third conductive means to the fourth conductive means.
Claim 3
Dependent Claim
35 words
The combination according to claim 1 further including first and second emitter-follower circuit means coupled with the collector electrodes of the first and second transistors, respectively, for providing first and second outputs of opposite phase.
Claim 4
Dependent Claim
70 words
The combination according to claim 1 further including a plurality of second transistors, each of the second transistors having emitter, base, and collector electrodes, with each collector electrode coupled with the second resistance means and each emitter electrode coupled with the first junction point; and a plurality of signal input means each coupled with the base electrode of a different one of the second transistors for applying input signals thereto.
Claim 5
Dependent Claim
59 words
The combination according to claim 3 further including third and fourth transistors, each having emitter, base, and collector electrodes, with the base electrodes thereof coupled with the collector electrodes of the first and second transistors, respectively, the collector electrodes thereof coupled with the first supply terminal, and the emitter electrodes thereof coupled in circuit with the second supply terminal.
Claim 6
Dependent Claim
17 words
The combination according to claim 4 wherein all of the transistors are of the same conductivity type.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-24 | 1976-04-24 | 1976-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-24 | 1980-04-24 | 1980-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-24 | 1984-04-24 | 1984-10-24 | $7700.00 | Window Closed / Lapsed |