Threshold logic overflow detector

Claim 2

A net overflow detector circuit for first and second adder circuits and a multiplier circuit, the detector circuit comprising first means for detecting a partial overflow of either one of two polarities and produced by the first adder circuit, second means for detecting a partial overflow of either one of two polarities and produced by the second adder circuit, third means for detecting a partial overflow of either one of two polarities and produced by the multiplier circuit, and means responsive to the first, second, and third detecting means for detecting all net overflow conditions resulting from all possible combinations of overflow from the first and second adder circuits and the multiplier circuit.

Claim 3

An overflow detector circuit in accordance with claim 1 further comprising first, second, third, and fourth busses included within the net overflow detecting means, means producing first and second clock signals, said first, second, and third detecting means, each including a first circuit responsive to the first clock signal for storing a positive overflow and for conducting a unit of current to one or the other of the first and second busses, and a second circuit responsive to the first clock signal for storing a negative overflow and for conducting a unit of current to one or the other of the third and fourth busses, means responsive to the units of current conducted through the first bus for producing a predetermined potential thereon, means responsive to the units of current conducted through the second bus for producing a predetermined potential thereon, means responsive to the units of current conducted through the third bus for producing a predetermined potential thereon, and means responsive to the units of current conducted through the fourth bus for producing a predetermined potential thereon.

Claim 4

A net overflow detector circuit in accordance with claim 2 further comprising a source of first reference potential, the net overflow detecting means further comprising means comparing the potential of the first bus with the first reference potential and steering a unit of current to the fourth bus when at least one unit of current is conducted through the first bus, and means comparing the potential of the third bus with the first reference potential and steering a unit of current to the second bus when at least one unit of current is conducted through the third bus.

Claim 5

A net overflow detector circuit in accordance with claim 3 further comprising a source of second reference potential, the net overflow detecting means further comprising means responsive to the second clock signal for comparing the potential of the second bus with the second reference potential and for storing a ''''0'''' except when less than three units of current are conducted through the second bus, and means responsive to the second clock signal for comparing the potential of the fourth bus with the second reference potential and for storing a ''''0'''' except when less than three units of current are conducted through the fourth bus.

Claim 6

A net overflow detector circuit in accordance with claim 2 further comprising a source of first reference potential, the net overflow detecting means further comprising means comparing the potential of the first bus with the first reference potential and steering a unit of current to the fourth bus when at least three units of current are conducted through the first bus, and means comparing the potential of the third steering bus with the first reference potential and steeriNg a unit of current to the second bus when at least three units of current are conducted through the third bus.

Claim 7

A net overflow detector circuit in accordance with claim 5 further comprising a source of second reference potential, the net overflow detecting means further comprising first bistable means responsive to the potential of the second bus and the second reference potential for assuming a first stable state when less than two units of current are conducted through the second bus and for assuming a second table state when at least two units of current are conducted through the second bus, and second bistable means responsive to the potential of the fourth bus and the second reference potential for assuming a first stable state when less than two units of current are conducted through the fourth bus and for assuming a second stable state when at least two units of current are conducted through the fourth bus.

Claim 8

An adder overflow detector comprising means producing first, second, and third clock signals, means responsive to the first clock signal for storing a sign bit of an addend code word, means responsive to the first clock signal for storing a sign bit of an augend code word, means responsive to the second clock signal for storing a sign bit of a sum code word produced by the adder in response to the addend and augend code words, first and second busses connected to the three storing means, the storing means each comprising bistable means for storing information, and steering means responsive to the clock signals and the state of the bistable means for steering a unit of current to one or the other of the busses, means responsive to the units of current conducted through the first bus for producing a predetermined potential thereon, means responsive to the units of current conducted through the second bus for producing a predetermined potential thereon, a source of reference potential, means responsive to the third clock signal for comparing the potential of the first bus with the reference potential and for storing a ''''1'''' only when three units of current are conducted through the first bus, and means responsive to the third clock signal for comparing the potential of the second bus with the reference potential and for storing a ''''1'''' only when the three units of current are conducted through the second bus.

Claim 9

An adder overflow detector comprising means producing first, second, and third clock signals, means responsive to the first clock signal for storing a sign bit of an addend code word, means responsive to the first clock signal for storing a sign bit of an augend code word, means responsive to the second clock signal for storing a sign bit of a sum code word produced by the adder in response to the addend and augend code words, first and second busses connected to the three storing means, the storing means each comprising bistable means for storing information, and steering means responsive to the clock signals and the state of the bistable means for steering a unit of current to one or the other of the busses, means responsive to the units of current conducted through the first bus for producing a predetermined potential thereon, means responsive to the units of current conducted through the second bus for producing a predetermined potential thereon, a source of reference potential, means responsive to the third clock signal for comparing the potential of the first bus with the reference potential and for storing a ''''1'''' only when three units of current are conducted through the first bus, and means responsive to the third clock signal for comparing the potential of the second bus with the reference potential and for storing a ''''1'''' only when the three units of current are conducted through the second bus.

Claim 10

An adder overflow detector comprising first and second busses, means for storing an addend sign bit and for steering a unit of current to one or the other of the first and second busses depending upon the polarity of the addend sign bit, means for storing an augend sign bit and for steering a unit of current to one or the other of the first and second busses depending upon the polarity of the augend sign bit, means for storing a sum sign bit and for steering a unit of current to one or the other of the first and second busses depending upon the polarity of the sum sign bit, means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon, a reference potential, bistable means responsive to the reference potential and to the potential of the first bus for assuming a first stable state when no unit of current is conducted in the first bus and for assuming a second stable state when at least one unit of current is conducted in the first bus, and bistable means responsive to the reference potential and to the potential of the second bus for assuming a first stable state when no unit of current is conducted in the second bus and for assuming a second stable state when at least one unit of current is conducted in the second bus.

Claim 11

An adder overflow detector comprising first and second busses, means for storing an addend sign bit and for steering a unit of current to one or the other of the first and second busses depending upon the polarity of the addend sign bit, means for storing an augend sign bit and for steering a unit of current to one or the other of the first and second busses depending upon the polarity of the augend sign bit, means for storing a sum sign bit and for steering a unit of current to one or the other of the first and second busses depending upon the polarity of the sum sign bit, means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon, a reference potential, bistable means responsive to the reference potential and to the potential of the first bus for assuming a first stable state when no unit of current is conducted in the first bus and for assuming a second stable state when at least one unit of current is conducted in the first bus, and bistable means responsive to the reference potential and to the potential of the second bus for assuming a first stable state when no unit of current is conducted in the second bus and for assuming a second stable state when at least one unit of current is conducted in the second bus.

Claim 12

A multiplier overflow detector comprising means producing first and second clock signals, first and second means responsive to the first clock signal for storing a sign bit of a magnitude code word from tHe multiplier, third means responsive to the first clock signal for storing a product sign bit of the output code word, a first bus connected to the first and third storing means, a second bus connected to the second and third storing means, the storing means each comprising bistable means for storing information, and steering means responsive to the first clock signal and the state of the bistable means for selectively steering a unit of current to the connected bus, means responsive to the units of current conducted through the first bus for producing a predetermined potential thereon, means responsive to the units of current conducted through the second bus for producing a predetermined potential thereon, a source of reference potential, means responsive to the second clock signal for comparing the potential of the first bus with the reference potential and for storing a ''''1'''' only when two units of current are conducted through the first bus, and means responsive to the second clock signal for comparing the potential of the second bus with the reference potential and for storing ''''1'''' only when two units of current are conducted through the second bus.

Claim 13

A multiplier overflow detector comprising means producing first and second clock signals, first and second means responsive to the first clock signal for storing a sign bit of a magnitude code word from tHe multiplier, third means responsive to the first clock signal for storing a product sign bit of the output code word, a first bus connected to the first and third storing means, a second bus connected to the second and third storing means, the storing means each comprising bistable means for storing information, and steering means responsive to the first clock signal and the state of the bistable means for selectively steering a unit of current to the connected bus, means responsive to the units of current conducted through the first bus for producing a predetermined potential thereon, means responsive to the units of current conducted through the second bus for producing a predetermined potential thereon, a source of reference potential, means responsive to the second clock signal for comparing the potential of the first bus with the reference potential and for storing a ''''1'''' only when two units of current are conducted through the first bus, and means responsive to the second clock signal for comparing the potential of the second bus with the reference potential and for storing ''''1'''' only when two units of current are conducted through the second bus.

Claim 14

A multiplier overflow detector comprising first and second busses, first and second means for storing a sign bit of a magnitude code word from the multiplier, the first means for selectively steering a unit of current to the first bus and the second means for selectively steering a unit of current to the second bus, both depending upon the polarity of the magnitude sign bit, means for storing a product sign bit of the output code word and for steering a unit of current to the first or second busses depending upon the polarity of the product sign bit, means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon, a reference potential, bistable means responsive to the reference potential and to the potential on the first bus for assuming a first stable state when no unit of current is conducted through the first bus and for assuming a second stable state when at least one unit of current is conducted through the first bus, and bistable means responsive to the reference potential and to the potential on the second bus for assuming a first stable state when no unit of current is conducted through the second bus and for assuming a second stable state when at least one unit of current is conducted through the second bus.

Claim 15

A multiplier overflow detector comprising first and second busses, first and second means for storing a sign bit of a magnitude code word from the multiplier, the first means for selectively steering a unit of current to the first bus and the second means for selectively steering a unit of current to the second bus, both depending upon the polarity of the magnitude sign bit, means for storing a product sign bit of the output code word and for steering a unit of current to the first or second busses depending upon the polarity of the product sign bit, means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon, a reference potential, bistable means responsive to the reference potential and to the potential on the first bus for assuming a first stable state when no unit of current is conducted through the first bus and for assuming a second stable state when at least one unit of current is conducted through the first bus, and bistable means responsive to the reference potential and to the potential on the second bus for assuming a first stable state when no unit of current is conducted through the second bus and for assuming a second stable state when at least one unit of current is conducted through the second bus.

Claim 16

A multiplier overflow detector comprising first and second busses, first and second means for storing a sign bit of a magnitude code word from the multiplier, the first means for selectively steering a unit of current to the first bus and the second means for selectively steering a unit of current to the second bus, both depending upon the polarity of the magnitude sign bit, means for storing a product sign bit of the output code word and for steering a unit of current alternatively to the first or second bus depending upon the polarity of the product sign bit, means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon, a reference potential, bistable means responsive to the reference potential and to the potential on the first bus for assuming a first stable state when two units of current are conducted through the first bus and for assuming a second stable state when less than two units of current are conducted through the first bus, and bistable means responsive to the reference potential and to the potential on the second bus for assuming a first stable state when two units of current are conducted through the second bus and for assuming a second stable state when less than two units of current are conducted through the second bus.

Claim 17

A multiplier overflow detector comprising first and second busses, first and second means for storing a sign bit of a magnitude code word from the multiplier, the first means for selectively steering a unit of current to the first bus and the second means for selectively steering a unit of current to the second bus, both depending upon the polarity of the magnitude sign bit, means for storing a product sign bit of the output code word and for steering a unit of current alternatively to the first or second bus depending upon the polarity of the product sign bit, means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon, a reference potential, bistable means responsive to the reference potential and to the potential on the first bus for assuming a first stable state when two units of current are conducted through the first bus and for assuming a second stable state when less than two units of current are conducted through the first bus, and bistable means responsive to the reference potential and to the potential on the second bus for assuming a first stable state when two units of current are conducted through the second bus and for assuming a second stable state when less than two units of current are conducted through the second bus.

Claim 18

An adder overflow detector comprising first and second busseS, means for storing a first addend sign bit and for steering a unit of current to one or the other of the first and second busses depending upon the polarity of the first addend sign bit, means for storing a second addend sign bit and for steering a unit of current to one or the other of the first and second busses depending upon the polarity of the second addend sign bit, means for storing a sum sign bit and for steering a unit of current to one or the other of the first and second busses depending upon the polarity of the sum sign bit, means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon, a reference potential, bistable means responsive to the reference potential and to the potential of the first bus for assuming a first stable state when three units of current are conducted in the first bus and for assuming a second stable state when less than three units of current are conducted in the first bus, and bistable means responsive to the reference potential and to the potential of the second bus for assuming a first stable state when three units of current are conducted in the second bus and for assuming a second stable state when less than three units of current are conducted in the second bus.

Claim 19

An adder overflow detector comprising first and second busseS, means for storing a first addend sign bit and for steering a unit of current to one or the other of the first and second busses depending upon the polarity of the first addend sign bit, means for storing a second addend sign bit and for steering a unit of current to one or the other of the first and second busses depending upon the polarity of the second addend sign bit, means for storing a sum sign bit and for steering a unit of current to one or the other of the first and second busses depending upon the polarity of the sum sign bit, means responsive to the units of current conducted through the first and second busses for producing predetermined potentials thereon, a reference potential, bistable means responsive to the reference potential and to the potential of the first bus for assuming a first stable state when three units of current are conducted in the first bus and for assuming a second stable state when less than three units of current are conducted in the first bus, and bistable means responsive to the reference potential and to the potential of the second bus for assuming a first stable state when three units of current are conducted in the second bus and for assuming a second stable state when less than three units of current are conducted in the second bus.