Telemetering remote recording unit

Claim 3

The system as defined in claim 1 in which said storage register includes: first and second latch circuits each having an input point, an output point and a control point; said first and second latch circuits each being responsive to a first signal condition at said respective control points for providing a conductive path from said respective input points to said respective output points and to a second signal condition at said respective control points for providing a non-conductive condition between said respective input points and said respective output points, said first and second latch circuits being further responsive to said signal condition at said respective control points changing from said first signal condition to said second signal condition for maintaining the signal condition at said respective output points not withstanding further changes in the signal condition at said respective input points until said signal condition at said respective control points revert to said first signal condition; means for connecting said output point of said first latch circuit to said input point of said second latch circuits said input point of said first latch circuit serving as said input terminal; and means responsive to control signals applied to said control terminal for successively applying (1) said first signal condition to said control points of said first and second latch circuit during a first time interval, (2) said first signal condition to said control point of said first latch circuit and said second signal condition to said control point of said second latch circuit during a third time interval.

Claim 4

The combination as defined in claim 2 in which said successive applying means includes: a shift register having first and second shift register stages for shifting level signals applied thereto from said first stage to said second stage; means for connecting said first stage of said shift register to said control point of said second latch circuit; and means for connecting said second stage of said shift register to said control point of said first latch circuit.

Claim 5

The combination as defined in claim 3 also including: means for normally applying a first level signal to said shift register, responsive to said information signal applying means for applying a second level signal to said shift register.

Claim 6

The system as defined in claim 4 also including: a plurality of latch circuits connected in cascade with each other and with said first and second latch circuits, each of said plurality having a control point; the last oF said plurality of latch circuits having an output point which serves as said output terminal; and said shift register has one stage for each latch circuit, each of said shift register stages being connected to a control point of one of said latch circuits.

Claim 7

The system as defined in claim 5 in which: said input terminal is a multi-contact terminal and said output terminal is a multi-contact terminal; each of said latch circuits have a plurality of input points and a plurality of output points, each of said respective input points being associated with one of said respective output points, said contact point controlling the electrical relationship between each pair of input points and output points in a like manner; said system also including: means for connecting each of said output points of said first latch circuit to one of said input points of said second latch circuit.

Claim 8

In combination: an ''''N'''' stage shift register for storing and shifting data bits in the form of ''''1''s'''' and 0''s,'''' ''''N'''' being an integer of three or more, said shift register being responsive to a clock signal for receiving applied data bits into a first of said ''''N'''' stages and advancing data bits stored in each of said ''''N'''' stages to a next succeeding stage; said shift register being further responsive to a transfer signal for receiving data bits in parallel into two or more of said ''''N'''' stages and inserting a predetermined data bit into a predetermined one of said ''''N'''' stages, said bits received in response to said transfer signal overriding said bits advanced by said clock signal; a clock for providing said clock signal; means for normally applying a signal level indicative of a data bit different from said predetermined data bit to said first stage of said shift register responsive to said transfer signal for applying a signal level indicative of said predetermined data bit to said first stage of said transfer signal; means responsive to the simultaneous occurrence of a data bit different than said predetermined data bit being present at said predetermined one and said ''''N'''' stages and two particular other of said ''''N'''' stages for providing said transfer signal; means for providing said data bits in parallel, said data bits in parallel providing means including: first and second multiposition switches, each of said switches having a wiper arm and a plurality of contacts; means for connecting each of said plurality of contacts on said second multiposition switch; means for connecting said contacts to said ''''N'''' stage shift resistor; means responsive to a start signal for sequentially applying a voltage signal to said wiper arms of said first and second multiposition switches; means for generating a first transmittable signal; means for generating a second transmittable signal; means responsive to information stored in one of said stages of said ''''N'''' stage shift register for providing one of said first and second transmittable signals; a switched telephone network having first and second access points; means responsive to signals received at said first access points of said switch telephone network for providing said start signal; and means for applying said one of said first and second transmittable signals to said first access point of said switched telephone network.

Claim 9

In combination: an ''''N'''' stage shift register for storing and shifting data bits in the form of ''''1''s'''' and 0''s,'''' ''''N'''' being an integer of three or more, said shift register being responsive to a clock signal for receiving applied data bits into a first of said ''''N'''' stages and advancing data bits stored in each of said ''''N'''' stages to a next succeeding stage; said shift register being further responsive to a transfer signal for receiving data bits in parallel into two or more of said ''''N'''' stages and inserting a predetermined data bit into a predetermined one of said ''''N'''' stages, said bits received in response to said transfer signal overriding said bits advanced by said clock signal; a clock for providing said clock signal; means for normally applying a signal level indicative of a data bit different from said predetermined data bit to said first stage of said shift register responsive to said transfer signal for applying a signal level indicative of said predetermined data bit to said first stage of said transfer signal; means responsive to the simultaneous occurrence of a data bit different than said predetermined data bit being present at said predetermined one and said ''''N'''' stages and two particular other of said ''''N'''' stages for providing said transfer signal; means for providing said data bits in parallel, said data bits in parallel providing means including: first and second multiposition switches, each of said switches having a wiper arm and a plurality of contacts; means for connecting each of said plurality of contacts on said second multiposition switch; means for connecting said contacts to said ''''N'''' stage shift resistor; means responsive to a start signal for sequentially applying a voltage signal to said wiper arms of said first and second multiposition switches; means for generating a first transmittable signal; means for generating a second transmittable signal; means responsive to information stored in one of said stages of said ''''N'''' stage shift register for providing one of said first and second transmittable signals; a switched telephone network having first and second access points; means responsive to signals received at said first access points of said switch telephone network for providing said start signal; and means for applying said one of said first and second transmittable signals to said first access point of said switched telephone network.

Claim 10

The combination as defined in claim 7 in which said first access point of said switched telephone network is a numbered telephone line, said combination also including: a storage register having an input terminal, an output terminal and a control terminal, said storage register being responsive to a control signal applied to said control terminal for storing data signals applied at said input terminal and providing data signals stored therein at said output terminal in a sequential mode; a punch card duplicAting machine for transferring information including a number of one of said telephone lines from a first punch card to a second punch card and providing (1) a data signal indicative of said number of said one of said telephone lines to said input terminal of said storage register (2) a control signal to said control terminal and (3) a second transfer signal indicating that said data signal indicative of said number of said one of said telephone lines has been provided, said machine being responsive to a punch signal for applying a control signal to said control terminal and punching information supplied on an information receiving terminal onto said second punch card; an automatic calling unit responsive to said second transfer signal (1) for applying a control signal to said control terminal of said storage register, then (2) receiving said data signals sequentially from said storage register and (3) outpulsing said data signals to said second access point of said switch telephone network; means responsive to said storage register receiving said signals on said second access point of said switched telephone network for providing said punch signal; and means for connecting said output terminal of said storage register to said information receiving terminal.

Claim 11

The combination as defined in claim 8 in which said storage register includes: first and second latch circuits each having an input point, an output point and a control point; said first and second latch circuits each being responsive to a first signal condition at said respective control points for providing a conductive path from said respective input points to said respective output points and to a second signal condition at said respective control points for providing a non-conductive condition between said respective input points and said respective output points, said first and second latch circuits being further responsive to said signal condition at said respective control points changing from said first signal condition to said second signal condition for maintaining the signal condition at said respective output points not withstanding further changes in the signal condition at said respective input points until said signal condition at said respective control points revert to said first signal condition; means for connecting said output point of said first latch circuit to said input point of said second latch circuits said input point of said first latch circuit serving as said input terminal; and p1 means responsive to control signals applied to said control terminal for successively applying (1) said first signal condition to said control points of said first and second latch circuit during a first time interval, (2) said first signal condition to said control point of said first latch circuit and said second signal condition to said control point of said control point of said second latch circuit during a third time interval.