Patent US3699567A successfully refreshed from Google Patents.
US3699567A
Expired / Lapsed
US
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Analog code conversion system
Assignee: Fujitsu Ltd
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Filing: 1970-12-09
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Granted: 1972-10-17
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Expires: 1990-12-09
Abstract
Abstract A code conversion system converts analog input signals to multinary code output signals. A polarity detector and comparator determines the polarity of an input signal and compares the input signal with reference signals. The polarity detector and comparator provide a multinary code output signal in accordance with the polarity and comparison. An amplitude divider divides the input signal in amplitude in a determined manner into a determined number of divided portions of equal amplitude and positions the divided portions of the input signal adjacent each other to lengthen the time duration of the divided portions. An amplifier amplifies the output signal of the amplitude divider a number of times equal to the determined number of divided portions. A time delay prevents overlap of the signal at the output of the amplifier with the signal supplied to the input of the amplitude divider. The amplitude divider, the amplifier and the time delay are connected in series circuit arrangement in a closed loop between the input of the system and the input of the polarity detector and comparator.
Inventors
- 👤 Zen Iti Kiyasu
- 👤 Masao Kawashima
- 👤 Shunroku Sasaki
- 👤 Yukihiko Mineshima
- 👤 Shyoichi Kurita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 05:59
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/44
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
301 words
A code conversion system for converting analog input signals to multinary code output signals of the order n, where n > 2, said code conversion system comprising reference means for providing n- 1 equispaced reference signals within the range of the analog input signals providing n voltage zones; polarity detector and comparator means for determining the polarity of a signal and comparing the analog input signals with said reference signals and for producing any of n different signals in accordance with which voltage zone the input signal level lies in; input means connected to the input of said polarity detector and comparator means for supplying an analog input signal to the input of said polarity detector and comparator means; amplitude dividing means for converting the analog input signal to an additional analog signal having a value corresponding linearly to the proximity of the analog input signal to the nearest of said reference signals, said amplitude dividing means having an input connected to said input means and an output; amplifying means for amplifying the additional analog signal so that the voltage range at the output of the amplitude dividing means is the same as the range of the analog input signal, said amplifying means having an input connected to the output of said amplitude dividing means and an output; time delay means having an input connected to the output of said amplifying means and an output connected to the input of said amplitude dividing means for preventing overlap of the signal at the output of said amplifying means with the signal supplied to the input of said amplitude dividing means, said amplitude dividing means, said amplifying means and said time delay means being connected in a closed loop between said input means and the input of said polarity detector and comparator means.
Claim 2
Dependent Claim
301 words
A code conversion system for converting analog input signals to multinary code output signals of the order n, where n > 2, said code conversion system comprising reference means for providing n- 1 equispaced reference signals within the range of the analog input signals providing n voltage zones; polarity detector and comparator means for determining the polarity of a signal and comparing the analog input signals with said reference signals and for producing any of n different signals in accordance with which voltage zone the input signal level lies in; input means connected to the input of said polarity detector and comparator means for supplying an analog input signal to the input of said polarity detector and comparator means; amplitude dividing means for converting the analog input signal to an additional analog signal having a value corresponding linearly to the proximity of the analog input signal to the nearest of said reference signals, said amplitude dividing means having an input connected to said input means and an output; amplifying means for amplifying the additional analog signal so that the voltage range at the output of the amplitude dividing means is the same as the range of the analog input signal, said amplifying means having an input connected to the output of said amplitude dividing means and an output; time delay means having an input connected to the output of said amplifying means and an output connected to the input of said amplitude dividing means for preventing overlap of the signal at the output of said amplifying means with the signal supplied to the input of said amplitude dividing means, said amplitude dividing means, said amplifying means and said time delay means being connected in a closed loop between said input means and the input of said polarity detector and comparator means.
Claim 3
Dependent Claim
35 words
A code conversion system as claimed in claim 1, wherein the input of said amplitude dividing means is connected to a common point between said input means and the output of said time delay means.
Claim 4
Dependent Claim
19 words
A code conversion system as claimed in claim 1, wherein said multinary code is a code of order 3.
Claim 5
Independent Claim
150 words
A method for converting analog input signals to multinary code output signals of the order n, where n > 2, comprising the steps of comparing an input signal with reference signals; discriminating the polarity of the input signal; producing a multinary code output signal in accordance with the polarity and comparison; feeding the input signal into a closed loop; converting the analog input signal to an additional analog signal having a value corresponding linearly to the proximity of the analog input signal to the nearest of said reference signals; amplifying the additional analog signal so that the voltage range amplified is the same as the range of the analog input signal in the closed loop; delaying the amplified additional analog signal to prevent overlap of the additional analog signal with the analog input signal; and feeding the delayed additional analog signal to the closed loop for reconverting, reamplifying, and redelaying.
Claim 6
Independent Claim
150 words
A method for converting analog input signals to multinary code output signals of the order n, where n > 2, comprising the steps of comparing an input signal with reference signals; discriminating the polarity of the input signal; producing a multinary code output signal in accordance with the polarity and comparison; feeding the input signal into a closed loop; converting the analog input signal to an additional analog signal having a value corresponding linearly to the proximity of the analog input signal to the nearest of said reference signals; amplifying the additional analog signal so that the voltage range amplified is the same as the range of the analog input signal in the closed loop; delaying the amplified additional analog signal to prevent overlap of the additional analog signal with the analog input signal; and feeding the delayed additional analog signal to the closed loop for reconverting, reamplifying, and redelaying.
Claim 7
Dependent Claim
18 words
A method as claimed in claim 4, further comprising supplying reference signals for comparison with the input signal.
References Cited (Backward Citations)
US2832827A
Cited
US3259896A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-17 | 1976-04-17 | 1976-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-17 | 1980-04-17 | 1980-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-17 | 1984-04-17 | 1984-10-17 | $7700.00 | Window Closed / Lapsed |