Patent US3699538A successfully refreshed from Google Patents.
US3699538A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logical circuit
Assignee: US Philips Corp
•
Filing: 1970-09-17
•
Granted: 1972-10-17
•
Expires: 1990-09-17
Abstract
Abstract Logical circuit in an envelope having a given number of input terminals, the number of applied input signals exceeding the number of input terminals. Of the input signals applied in order of succession to an input terminal an earlier signal is stored via a gate controlled by a control-signal in a storage element so that this signal in common with a signal applied later to said input terminal becomes available at a group of logical elements of the logical circuit, in which group the signals can be processed simultaneously (FIG. 1).
Inventors
- 👤 Hendrik Arie Van Essen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:07
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; G; G11; G11C; G11C7/00; G11C7/10; G11C7/1006; G11C7/1078; H03K3/0372
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
170 words
A logic circuit module for processing at least two serially transmitted groups of n signals, comprising a terminal on the module for receiving control signals, n terminals for receiving the groups of binary information signals, at least n gates each having an input connected to the control signal terminal and each having a further input connected to a different one of the n binary information input terminals, a separate storage device connected to an output of each gate for storing a binary information signal passed through the associated gate in response to a control signal on the control signal terminal, a logic matrix, means for connecting an output of each storage element to a separate input of the logic matrix, and a separate means for connecting each information signal input terminal to a separate input of the logic matrix, whereby two groups of n information signals received on n input terminals of the module maybe processed within the module by a logic matrix having at least two n input terminals.
Claim 2
Dependent Claim
170 words
A logic circuit module for processing at least two serially transmitted groups of n signals, comprising a terminal on the module for receiving control signals, n terminals for receiving the groups of binary information signals, at least n gates each having an input connected to the control signal terminal and each having a further input connected to a different one of the n binary information input terminals, a separate storage device connected to an output of each gate for storing a binary information signal passed through the associated gate in response to a control signal on the control signal terminal, a logic matrix, means for connecting an output of each storage element to a separate input of the logic matrix, and a separate means for connecting each information signal input terminal to a separate input of the logic matrix, whereby two groups of n information signals received on n input terminals of the module maybe processed within the module by a logic matrix having at least two n input terminals.
Claim 3
Dependent Claim
91 words
A logic circuit as cLaimed in claim 1, wherein the separate means for connecting each information signal input terminal to a separate input of the logic matrix comprises n auxiliary gates each having an input connected to a separate information input terminal of the module and having a further input connected to the control signal terminal of the module, and means for inverting the control signals to the auxiliary gates whereby the auxiliary gates and the first gates are inversely controlled by the signals on the control terminal of the module.
Claim 4
Dependent Claim
31 words
A circuit as claimed in claim 2, further comprising an auxiliary group of storage elements each connected between an output of an auxiliary gate and an input of the logic matrix.
Claim 5
Dependent Claim
35 words
A logic circuit as claimed in claim 1 wherein the storage element comprises a master-slave flip-flop, and wherein the logic circuit further comprises a clock-pulse input terminal on the module connected to the master-slave flip-flop.
Claim 6
Dependent Claim
43 words
A logic circuit as claimed in claim 1, wherein the storage element is a master-slave flip-flop having a clock-pulse input terminal, and further comprising means for connecting the clock-pulse input terminal of the master-slave flip-flop to the control-signal input terminal of the module.
Claim 7
Dependent Claim
39 words
A circuit module as claimed in claim 1, further comprising means for connecting the control terminal of the module to the logic matrix, and wherein the logic matrix is responsive to signals on the control input of the module.
References Cited (Backward Citations)
US3069660A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-17 | 1976-04-17 | 1976-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-17 | 1980-04-17 | 1980-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-17 | 1984-04-17 | 1984-10-17 | $7700.00 | Window Closed / Lapsed |