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US3699535A
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Memory look-ahead connection arrangement for writing into an unoccupied address and prevention of reading out from an empty address
Assignee: Raytheon Co
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Filing: 1971-02-01
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Granted: 1972-10-17
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Expires: 1991-02-01
Abstract
Abstract A memory interconnection or wiring arrangement which prevents a valid word in the memory from being destroyed by overwriting and also prevents an empty or obsolete memory word from being read out, thereby conserving both time and power. The arrangement involves the employment of one or two additional memory planes or additional bistable storage elements and circuitry which are used to store tag words which indicate whether a forthcoming memory address contains valid or obsolete information. In this arrangement, a tag or status indication signal is written in the additional memory elements to indicate that a word has been written into the current address location. Simultaneously, the state of a second tag or status indicating signal is read or detected to determine whether the forthcoming address location is empty or contains valid information. The detection of this tag during read out is used to determine whether the reading or writing process should continue, stop or search for another address location. The arrangement can be used with core memories, solid state memories, plated wire and thin film memories or any other device in which the interconnection or wiring between the main memory and additional storage and electronic elements can be controlled.
Inventors
- 👤 Stanley Frank Klein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:37
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
149 words
A memory system having writing means for storing and reading means for extracting digital data, said system comprising a magnetic matrix memory made up of rows and columns of storage elements to form a plurality of memory planes, each element in a plane exhibiting plural states of magnetic stability, a first additional memory plane adapted to store a status indicating bit in response to a word being written into a location of said memory planes, a second additional memory plane adapted to read out from said second additional memory plane a formerly stored second status indicating bit to determine whether or not a subsequent address location in said memory planes contains data, means in response to reading out the magnetic state of said second additional plane to generate a control signal, and means in response to said control signal to Determine the operation of said reading and writing means.
Claim 2
Dependent Claim
149 words
A memory system having writing means for storing and reading means for extracting digital data, said system comprising a magnetic matrix memory made up of rows and columns of storage elements to form a plurality of memory planes, each element in a plane exhibiting plural states of magnetic stability, a first additional memory plane adapted to store a status indicating bit in response to a word being written into a location of said memory planes, a second additional memory plane adapted to read out from said second additional memory plane a formerly stored second status indicating bit to determine whether or not a subsequent address location in said memory planes contains data, means in response to reading out the magnetic state of said second additional plane to generate a control signal, and means in response to said control signal to Determine the operation of said reading and writing means.
Claim 3
Dependent Claim
222 words
A memory system for storing and retrieving digital data, said system comprising a main memory matrix made up of bit columns and word rows of bit storage elements, each of said bit storage elements exhibiting plural states of stability, means to set said rows of bit storage elements to states representing respective words of data, a first auxiliary memory plane made up of columns and rows of storage elements and electrically interconnected with corresponding columns and rows of storage elements in said memory matrix, means for reading out a first status bit in said first auxiliary memory plane when a corresponding location in said main memory matrix is being written into, a second auxiliary memory plane made up of columns and rows of storage elements and electrically interconnected with corresponding succeeding columns of storage elements in said main memory matrix, means for storing a second status bit in said second auxiliary memory plane when a corresponding location in said main memory matrix contains usable data, means for detecting said first and second status bits, means in response to detection of said first status bit to inhibit the introduction of additional data into a subsequent address of said main memory matrix, and means in response to detection of said second status bit to inhibit writing of additional data from said main memory matrix.
Claim 4
Dependent Claim
222 words
A memory system for storing and retrieving digital data, said system comprising a main memory matrix made up of bit columns and word rows of bit storage elements, each of said bit storage elements exhibiting plural states of stability, means to set said rows of bit storage elements to states representing respective words of data, a first auxiliary memory plane made up of columns and rows of storage elements and electrically interconnected with corresponding columns and rows of storage elements in said memory matrix, means for reading out a first status bit in said first auxiliary memory plane when a corresponding location in said main memory matrix is being written into, a second auxiliary memory plane made up of columns and rows of storage elements and electrically interconnected with corresponding succeeding columns of storage elements in said main memory matrix, means for storing a second status bit in said second auxiliary memory plane when a corresponding location in said main memory matrix contains usable data, means for detecting said first and second status bits, means in response to detection of said first status bit to inhibit the introduction of additional data into a subsequent address of said main memory matrix, and means in response to detection of said second status bit to inhibit writing of additional data from said main memory matrix.
Claim 5
Dependent Claim
112 words
A memory system comprising a plurality of electrical elements connected in rows and columns to form a plurality of main memory planes, each electrical element in a plane exhibiting plural states of stability; input, output and word wires connected to each of said elements; an additional memory plane of elements having input and output wires coupled to corresponding wires on said main memory planes and word wires coupled to a corresponding preceding additional memory element to provide a status indicating signal; and means for detecting said status indicating signal to provide a control signal to halt entry of further data in a corresponding main memory plane subsequent to said additional memory plane.
Claim 6
Dependent Claim
112 words
A memory system comprising a plurality of electrical elements connected in rows and columns to form a plurality of main memory planes, each electrical element in a plane exhibiting plural states of stability; input, output and word wires connected to each of said elements; an additional memory plane of elements having input and output wires coupled to corresponding wires on said main memory planes and word wires coupled to a corresponding preceding additional memory element to provide a status indicating signal; and means for detecting said status indicating signal to provide a control signal to halt entry of further data in a corresponding main memory plane subsequent to said additional memory plane.
Claim 7
Dependent Claim
148 words
A memory system comprising a plurality of magnetic storage elements forming the rows and columns of a plurality of data storage planes, each storage element in a plane exhibiting plural states of magnetic stability; input, output and word windings on each of said elements; means in conjunction with signals on a predetermined input winding and signals on word windings to store data in the storage elements through which said input and word windings intersect; an additional memory plane connected to store a status indicating bit in response to transfer of information from said word windings to their respective corresponding preceding storage elements in conjunction with activation of selected input windings; means for detecting the presence of said status bit in the additional memory plane; and means in response to said detection to prevent the input of further data until data has been cleared from the corresponding memory location.
Claim 8
Dependent Claim
148 words
A memory system comprising a plurality of magnetic storage elements forming the rows and columns of a plurality of data storage planes, each storage element in a plane exhibiting plural states of magnetic stability; input, output and word windings on each of said elements; means in conjunction with signals on a predetermined input winding and signals on word windings to store data in the storage elements through which said input and word windings intersect; an additional memory plane connected to store a status indicating bit in response to transfer of information from said word windings to their respective corresponding preceding storage elements in conjunction with activation of selected input windings; means for detecting the presence of said status bit in the additional memory plane; and means in response to said detection to prevent the input of further data until data has been cleared from the corresponding memory location.
Claim 9
Dependent Claim
160 words
A memory system for storing and retrieving digital data according to the status of a memory location, said system comprising a memory matrix made up of bit columns and word rows of magnetic bit storage elements each of which exhibits plural states of stability, means to set said rows of bit storage elements to states representing respective words of data, an additional memory matrix made up of a pair of memory planes of elements having a plurality of states for accepting respective bits of a word, each element associated with a row of said bit storage elements, means for generating interrogation pulses to provide tag indicating means in one element of said additional memory matrix for indicating the status of a present data storing location and for interrogating another element for indicating the status of a subsequent data storing location of said memory matrix, and means responsive to said indicating means to inhibit the handlinG of data at said locations.
Claim 10
Dependent Claim
160 words
A memory system for storing and retrieving digital data according to the status of a memory location, said system comprising a memory matrix made up of bit columns and word rows of magnetic bit storage elements each of which exhibits plural states of stability, means to set said rows of bit storage elements to states representing respective words of data, an additional memory matrix made up of a pair of memory planes of elements having a plurality of states for accepting respective bits of a word, each element associated with a row of said bit storage elements, means for generating interrogation pulses to provide tag indicating means in one element of said additional memory matrix for indicating the status of a present data storing location and for interrogating another element for indicating the status of a subsequent data storing location of said memory matrix, and means responsive to said indicating means to inhibit the handlinG of data at said locations.
Claim 11
Dependent Claim
174 words
A memory system comprising a plurality of storage elements interconnected in rows and columns to form a plurality of memory planes, each element in a plane exhibiting plural states of stability; input, output and word wires on each of said element; an additional memory plane of elements having word wires coupled to corresponding word wires on said plurality of memory planes, said word wires adapted to store in said additional memory plane a status indicating bit in response to a word being written into said memory planes in conjunction with said input wires; means for detecting said status indicating bit in an element of said additional memory plane to provide a control signal; means for rewriting a second status indicating bit into said element of said additional memory plane; means for reading out a word from said plurality of memory planes as determined by said output wires on said elements; and means in response to said control signal to halt the introduction of an additional word into a subsequent address of said memory planes.
Claim 12
Dependent Claim
174 words
A memory system comprising a plurality of storage elements interconnected in rows and columns to form a plurality of memory planes, each element in a plane exhibiting plural states of stability; input, output and word wires on each of said element; an additional memory plane of elements having word wires coupled to corresponding word wires on said plurality of memory planes, said word wires adapted to store in said additional memory plane a status indicating bit in response to a word being written into said memory planes in conjunction with said input wires; means for detecting said status indicating bit in an element of said additional memory plane to provide a control signal; means for rewriting a second status indicating bit into said element of said additional memory plane; means for reading out a word from said plurality of memory planes as determined by said output wires on said elements; and means in response to said control signal to halt the introduction of an additional word into a subsequent address of said memory planes.
Claim 13
Dependent Claim
162 words
A memory system having a main memory storage means including a plurality of memory planes and an auxiliary memory storage means having at least one additional memory plane operatively coupled to said main memory storage means, means for address activating the memory locations of said auxiliary storage means and corresponding locations in said main memory storage means, means for writing data into an address of the main memory storage means and simultaneously writing a status indicating bit into a corresponding preceding address of said additional memory plane, said means for writing data adapted to actuate means for reading the corresponding succeeding location in said additional memory plane to detect the presence of a status bit adapted to indicate that the next address location of said main memory storage means contains data, and means in response to the presence of a status bit in said additional memory plane to prevent overwriting data into the corresponding address location of said main memory storage means.
Claim 14
Dependent Claim
162 words
A memory system having a main memory storage means including a plurality of memory planes and an auxiliary memory storage means having at least one additional memory plane operatively coupled to said main memory storage means, means for address activating the memory locations of said auxiliary storage means and corresponding locations in said main memory storage means, means for writing data into an address of the main memory storage means and simultaneously writing a status indicating bit into a corresponding preceding address of said additional memory plane, said means for writing data adapted to actuate means for reading the corresponding succeeding location in said additional memory plane to detect the presence of a status bit adapted to indicate that the next address location of said main memory storage means contains data, and means in response to the presence of a status bit in said additional memory plane to prevent overwriting data into the corresponding address location of said main memory storage means.
Claim 15
Dependent Claim
29 words
The apparatus of claim 7 in which additional means is provided for preventing reading out of used data from said next address location of said main memory storage means.
Claim 16
Dependent Claim
94 words
A memory system comprising a plurality of storage elements interconnected in rows and columns to form a plurality of memory planes, each element in a plane exhibiting plural states of stability; input, output and word windings on said elements, an additional memory plane of elements interconnected to corresponding preceding and subsequent elements of said plurality of memory planes; control means adapted to read out from said subsequent elements to prevent overwriting of data from said subsequent elements, said control means also including means for preventing reading out of obsolete data from said subsequent elements.
Claim 17
Dependent Claim
94 words
A memory system comprising a plurality of storage elements interconnected in rows and columns to form a plurality of memory planes, each element in a plane exhibiting plural states of stability; input, output and word windings on said elements, an additional memory plane of elements interconnected to corresponding preceding and subsequent elements of said plurality of memory planes; control means adapted to read out from said subsequent elements to prevent overwriting of data from said subsequent elements, said control means also including means for preventing reading out of obsolete data from said subsequent elements.
Claim 18
Dependent Claim
35 words
The apparatus of claim 9 in which means is provided for writing a status indicating tag into the preceding element of said additional memory plane during writing into elements of said plurality of memory planes.
Claim 19
Dependent Claim
133 words
In a memory system having a main memory storage means and a main storage address means for address activating the locations of said main memory storage means, the combination comprising an auxiliary memory storage means which is address activated by said address activating means for activating the locations of said auxiliary memory storage means, means associated with said auxiliary memory storage means to indicate the presence of data in a corresponding location in the main memory storage means, said auxiliary memory storage means adapted to indicate the status of the subsequent corresponding locations in the main memory storage means, and means in response to detection of data in corresponding present and subsequent locations in the main memory storage means to prevent introduction of data into such locations in the main memory storage means.
Claim 20
Dependent Claim
133 words
In a memory system having a main memory storage means and a main storage address means for address activating the locations of said main memory storage means, the combination comprising an auxiliary memory storage means which is address activated by said address activating means for activating the locations of said auxiliary memory storage means, means associated with said auxiliary memory storage means to indicate the presence of data in a corresponding location in the main memory storage means, said auxiliary memory storage means adapted to indicate the status of the subsequent corresponding locations in the main memory storage means, and means in response to detection of data in corresponding present and subsequent locations in the main memory storage means to prevent introduction of data into such locations in the main memory storage means.
Claim 21
Dependent Claim
145 words
A memory organization for a digital cOmputer comprising a main memory means, an auxiliary memory means of smaller capacity than said main memory means, coupled to said main memory means to receive information issued from said main memory means for tag indication, a determining means associated with said auxiliary memory means to determine the status of data stored in corresponding locations of said main memory means, said status determining means including status indicating means in conjunction with said auxiliary memory means to indicate the presence of data in subsequent corresponding locations in said main memory means, means responsive to an indication of data stored in said auxiliary memory means to prevent overwriting of additional data into said subsequent corresponding locations in the main memory means, and means to prevent initiating the reading out of obsolete data from a corresponding location in the main memory means.
Claim 22
Dependent Claim
145 words
A memory organization for a digital cOmputer comprising a main memory means, an auxiliary memory means of smaller capacity than said main memory means, coupled to said main memory means to receive information issued from said main memory means for tag indication, a determining means associated with said auxiliary memory means to determine the status of data stored in corresponding locations of said main memory means, said status determining means including status indicating means in conjunction with said auxiliary memory means to indicate the presence of data in subsequent corresponding locations in said main memory means, means responsive to an indication of data stored in said auxiliary memory means to prevent overwriting of additional data into said subsequent corresponding locations in the main memory means, and means to prevent initiating the reading out of obsolete data from a corresponding location in the main memory means.
Claim 23
Dependent Claim
112 words
A memory system comprising a plurality of storage elements connected in rows and columns to form a plurality of memory planes, each storage element in a plane exhibiting plural states of stability; input, output and word wires on each of said elements; an additional memory plane of storage elements having word wires coupled to corresponding word wires on said plurality of memory planes, each storage element in said additional memory plane coupled to a corresponding preceding element in said memory planes; and means for detecting the status of an element in said additional memory plane to provide a control signal indicative of the status of the corresponding portion of said memory planes.
Claim 24
Dependent Claim
112 words
A memory system comprising a plurality of storage elements connected in rows and columns to form a plurality of memory planes, each storage element in a plane exhibiting plural states of stability; input, output and word wires on each of said elements; an additional memory plane of storage elements having word wires coupled to corresponding word wires on said plurality of memory planes, each storage element in said additional memory plane coupled to a corresponding preceding element in said memory planes; and means for detecting the status of an element in said additional memory plane to provide a control signal indicative of the status of the corresponding portion of said memory planes.
Claim 25
Dependent Claim
233 words
A memory system comprising a plurality of storage elements interconnected in rows and columns to form a plurality of main memory planes, each storage element in a plane exhibiting plural states of stability; input, output and word wires on each of said elements; a first additional memory plane of storage elements having word wires coupled to corresponding word wires on said plurality of main memory planes, each storage element in said first additional memory plane coupled to corresponding elements in said main memory planes, and also coupled to a corresponding preceding element in a second additional memory plane, said word wires on said first and second additional memory planes adapted to store a status indicating bit in response to a word being written into said main memory planes in conjunction with said input wires; means for detecting said status indicating bit in an element of one of said additional memory planes to provide a control signal; means for rewriting a second status indicating bit into said one of said elements of one of said additional memory planes; means for reading out said word from said plurality of main memory planes as determined by said output wires on said elements of said plurality of main memory planes; and means in response to said control signal to halt the introduction of an additional word into said main memory planes by way of said input wires.
Claim 26
Dependent Claim
233 words
A memory system comprising a plurality of storage elements interconnected in rows and columns to form a plurality of main memory planes, each storage element in a plane exhibiting plural states of stability; input, output and word wires on each of said elements; a first additional memory plane of storage elements having word wires coupled to corresponding word wires on said plurality of main memory planes, each storage element in said first additional memory plane coupled to corresponding elements in said main memory planes, and also coupled to a corresponding preceding element in a second additional memory plane, said word wires on said first and second additional memory planes adapted to store a status indicating bit in response to a word being written into said main memory planes in conjunction with said input wires; means for detecting said status indicating bit in an element of one of said additional memory planes to provide a control signal; means for rewriting a second status indicating bit into said one of said elements of one of said additional memory planes; means for reading out said word from said plurality of main memory planes as determined by said output wires on said elements of said plurality of main memory planes; and means in response to said control signal to halt the introduction of an additional word into said main memory planes by way of said input wires.
Claim 27
Dependent Claim
40 words
The apparatus of claim 14 in which the rewriting means includes means for directing flow of current in a direction through one of said additional memory planes opposite to that of current flow during detection of a status indicating bit.
Claim 28
Dependent Claim
111 words
A memory system comprising main memory means, auxiliary memory means, a first location of said auxiliary memory means interconnected with said main memory means to store a status indicating bit when data is written into corresponding locations of said main memory means, a second location of said auxiliary memory means interconnected with said main memory means in a manner adapted to read out a status indicating bit on a forthcoming read out cycle of said main memory means, and control means actuated by read out of said status indicating bits to prevent overwriting of valid data and read out of obsolete data from corresponding subsequent locations of said main memory means.
Claim 29
Dependent Claim
111 words
A memory system comprising main memory means, auxiliary memory means, a first location of said auxiliary memory means interconnected with said main memory means to store a status indicating bit when data is written into corresponding locations of said main memory means, a second location of said auxiliary memory means interconnected with said main memory means in a manner adapted to read out a status indicating bit on a forthcoming read out cycle of said main memory means, and control means actuated by read out of said status indicating bits to prevent overwriting of valid data and read out of obsolete data from corresponding subsequent locations of said main memory means.
Claim 30
Dependent Claim
62 words
A memory system having a main memory and an auxiliary memory, address means coupling saiD main memory and said auxiliary memory means to store status signals in said auxiliary memory, said auxiliary memory having means to respond to present and forthcoming write in and read out signals from subsequent main memory locations to determine the presence of data in said main memory.
Claim 31
Dependent Claim
62 words
A memory system having a main memory and an auxiliary memory, address means coupling saiD main memory and said auxiliary memory means to store status signals in said auxiliary memory, said auxiliary memory having means to respond to present and forthcoming write in and read out signals from subsequent main memory locations to determine the presence of data in said main memory.
References Cited (Backward Citations)
US3328765A
Cited
US3365704A
Cited
US3398405A
Cited
US3405394A
Cited
US3440615A
Cited
US3599159A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-17 | 1976-04-17 | 1976-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-17 | 1980-04-17 | 1980-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-17 | 1984-04-17 | 1984-10-17 | $7700.00 | Window Closed / Lapsed |