Cellular arithmetic array

Claim 2

A clock driven cellular arithmetic array for storing binary words and preforming operations thereon comprising: a plurality of cells arranged in rows and columns; input means for supplying binary input signals to the columns of said array, and; a first and second means for controlling the operations of the cells of any row of the array; wherein the binary words stored in any row may be read-in or read-out simultaneously with the changing of any other word by an increment of one binary number during one clock pulse; each of said cells has three inputs and two outputs; one of said inputs being a bus connected in parallel to each of said cells in a particular row; the second of said inputs being operationally connected in series, the output of one cell being the input to the next cell; the first and second inputs being derived from the first and second means, and; the third input being derived from the input means; the two outputs of each of the cells being supplied one to the next cell in the same row as the cell supplying the output and the other to the next cell in the same column as that of the cell supplying the outputs; said one output being defined by the equation: Z'' Z(W + V) said other output being defined by the equation: U X + WZY where Z'' represents said one output, X, Z'' and W represent said third, second and one of said inputs, Y represents the memory state of said cell, and Z represents the inversion of Z.

Claim 3

A circuit for processing digital words comprising: a matrix array of a plurality of identical cells connected together to form rows and columns; an input register connected to each cell in the top row of said matrix array; an output register connected to each cell in the bottom row of said matrix array; first control register means connected directly to each of said plurality of identical cells and functioning to apply the same binary signal to every cell in a row, and; second control register means connected to said matrix array and functioning to applY the same signal directly to every cell in a row when the signal applied by said first control register means is of one binary value and to apply a signal directly to only one cell in a row when the signal applied by said first control register means is of the other binary value; wherein each cell comprises: a flip-flop having an output and three inputs, said output being 1 when set by one of said inputs, 0 when reset by a second of said inputs and changed when toggled by the third of said inputs; first, second and third AND gates connected to said set, toggle and reset controls of said flip-flop; a first output; a second output, and; circuit means connected to said first, second and third AND gates, to said first and second control register means, to the output of said flip-flop and to said first and second outputs and functioning to control said first and second outputs.

Claim 4

A circuit for processing digital words comprising: a matrix array of a plurality of identical cells connected together to form rows and columns; an input register connected to each cell in the top row of said matrix array; an output register connected to each cell in the bottom row of said matrix array; first control register means connected directly to each of said plurality of identical cells and functioning to apply the same binary signal to every cell in a row, and; second control register means connected to said matrix array and functioning to applY the same signal directly to every cell in a row when the signal applied by said first control register means is of one binary value and to apply a signal directly to only one cell in a row when the signal applied by said first control register means is of the other binary value; wherein each cell comprises: a flip-flop having an output and three inputs, said output being 1 when set by one of said inputs, 0 when reset by a second of said inputs and changed when toggled by the third of said inputs; first, second and third AND gates connected to said set, toggle and reset controls of said flip-flop; a first output; a second output, and; circuit means connected to said first, second and third AND gates, to said first and second control register means, to the output of said flip-flop and to said first and second outputs and functioning to control said first and second outputs.