Forward-acting error control system

Claim 2

In a communication system for communicating an input sequence of data signals over a communications channel, said system comprising a transmitter and a receiver coupled to the respective ends of said channel, the improvement comprising an encoder at said transmitter comprising an ordered plurality of adders, each having first and second input terminals and an output terminal, each of said adders comprising means for generating signals at said output terminal representative of the sum of signals appearing at said first and second input terminals, an equal plurality of memory devices, each of said devices having an input terminal and an output terminal, each of said memory devices being initially in a cleared state, means for applying data signals in said input sequence to said second input terminal of selected ones of said adders, means for connecting the output terminal of each of said memory devices to the first input terminal of a corresponding one of said adders, means for selectively connecting the input terminal of each of said memory devices to the output terminal of said corresponding one of said adders, whereby there is formed and stored in said memory devices a sequence of sums, said sequence of sums including an initial sum and successive updated sums of selected ones of said input sequence of data signals and previously stored sums, and means for periodically applying one of said updated sums to said channel to constitute parity signals associated with said input data signals.

Claim 3

A system in accordance with claim 1 wherein each of said adders is a modulo-2 adder.

Claim 4

A system in accordance with claim 2 further comprising means for periodically transferring the sum stored in each memory device, except the last, to another memory device.

Claim 5

A system in accordance with claim 3 wherein said means for periodically applying parity signals to said channel comprises means for applying the updated sum stored at the last of said memory devices to said channel.

Claim 6

A system in accordance with claim 4 further comprising means for initializing the contents of said memory device associated with each of said adders.

Claim 7

A system according to claim 5 further including encoder control means for generating signals to control said means for periodically applying one of said updated sums to said channel.

Claim 8

A system according to claim 6 wherein said means for applying data signals in said input sequence comprises means at each of said modulo-2 adders for selectively applying said input sequence of data signals to said second input terminal of each of said modulo-2 adders in response to signals from said encoder control means.

Claim 9

In a communications system for communicatinG an input sequence of data signals over a communications channel, said system comprising a transmitter and a receiver coupled to respective ends of said channel, said transmitter comprising means for generating and applying to said channel parity signals based on said data signals, wherein the improvement comprises an encoder at said receiver for generating parity signals in response to data signals received from said channel, said encoder comprising an ordered plurality of adders, each having first and second input terminals and an output terminal, each of said adders comprising means for generating signals at said output terminal representative of the sum of signals appearing at said first and second input terminals, an equal plurality of memory devices, each of said devices having an input terminal and an output terminal, each of said memory devices being initially in a cleared state, means for applying data signals in said input sequence to said second input terminal of selected ones of said adders, means for connecting the output terminal of each of said memory devices to the first input terminal of a corresponding one of said adders, means for selectively connecting the input terminal of each of said memory devices to the output terminal of said corresponding one of said adders, whereby there is formed and stored in said memory devices a sequence of sums, said sequence of sums including an initial sum and successive updated sums of selected ones of said data signals received from said channel and previously stored sums.

Claim 10

In a communications system for communicatinG an input sequence of data signals over a communications channel, said system comprising a transmitter and a receiver coupled to respective ends of said channel, said transmitter comprising means for generating and applying to said channel parity signals based on said data signals, wherein the improvement comprises an encoder at said receiver for generating parity signals in response to data signals received from said channel, said encoder comprising an ordered plurality of adders, each having first and second input terminals and an output terminal, each of said adders comprising means for generating signals at said output terminal representative of the sum of signals appearing at said first and second input terminals, an equal plurality of memory devices, each of said devices having an input terminal and an output terminal, each of said memory devices being initially in a cleared state, means for applying data signals in said input sequence to said second input terminal of selected ones of said adders, means for connecting the output terminal of each of said memory devices to the first input terminal of a corresponding one of said adders, means for selectively connecting the input terminal of each of said memory devices to the output terminal of said corresponding one of said adders, whereby there is formed and stored in said memory devices a sequence of sums, said sequence of sums including an initial sum and successive updated sums of selected ones of said data signals received from said channel and previously stored sums.

Claim 11

A system according to claim 8 further comprising means for comparing parity signals generated at said receiver with parity signals received from said channel.

Claim 12

A system according to claim 9 wherein each of said adders is a modulo-2 adder.

Claim 13

A system according to claim 10 further comprising encoder control means for generating control signals to control said means for comparing parity signals generated at said receiver with parity signals received from said channel.

Claim 14

A system according to claim 11 wherein said means for applying comprises means at each of said modulo-2 adders for selectively applying said signals from said channel to the second input terminal of said modulo-2 adders in response to control signals from said encoder control means.

Claim 15

A system according to claim 12 further including means for periodically transferring the sum stored at each memory device at each adder, except the last, to another memory device.

Claim 16

Apparatus according to claim 13 wherein said means for comparing parity signals generated at said receiver with parity signals received from said channel comprises means for simultaneously applying said updated sum at the last of said adders to said first input terminal of said last adder and the parity signal from said channel to said second input terminal of said last adder.

Claim 17

Apparatus according to claim 14 further including means at said receiver for inverting selected ones of said data signals received from said channel in response to said means for comparing parity signals generated at said receiver with parity signals received from said channel.

Claim 18

In a data transmission system including a transmission channel interconnecting a transmitter and a receiver for detecting and correcting error bursts of n bits in length in an input sequence of data signals from a data source, an encoder in said transmitter comprising, encoder control means a plurality of exclusive-OR circuits, each having first and second input terminals and an output terminal, a first set of encoder switches responsive to said encoder control means, one in each path connecting each of said encoder exclusive-OR first input terminals to said source of data signals, a plurality of n-stage shift registers for delaying and reapplying signals from each of said exclusive-OR output terminals to said second input terminal thereof, means responsive to Said encoder control means for transferring signals from selected ones of said shift registers to different selected ones of said shift registers, and means responsive to said encoder control means for applying signals stored in a selected one of said shift registers to said channel.

Claim 19

In a data transmission system including a transmission channel interconnecting a transmitter and a receiver for detecting and correcting error bursts of n bits in length in an input sequence of data signals from a data source, an encoder in said transmitter comprising, encoder control means a plurality of exclusive-OR circuits, each having first and second input terminals and an output terminal, a first set of encoder switches responsive to said encoder control means, one in each path connecting each of said encoder exclusive-OR first input terminals to said source of data signals, a plurality of n-stage shift registers for delaying and reapplying signals from each of said exclusive-OR output terminals to said second input terminal thereof, means responsive to Said encoder control means for transferring signals from selected ones of said shift registers to different selected ones of said shift registers, and means responsive to said encoder control means for applying signals stored in a selected one of said shift registers to said channel.

Claim 20

A system as in claim 16 further including a decoder in said receiver, comprising, decoder control means, a plurality of decoder exclusive-OR circuits each having first and second input terminals and an output terminal, a plurality of n-stage shift registers arranged to delay and reapply signals at each of said decoder exclusive-OR output terminals to the second input terminal thereof, a first set of decoder switches one at each decoder exclusive-OR circuit for selectively applying signals from said channel to said decoder exclusive-OR first input terminals in response to said decoder control means, means for applying signals from each of said shift registers, except one, to a different one of said shift registers, and means for generating syndrome signals in response to said signals stored in a selected one of said encoder shift registers applied to said decoder by means of said channel with signals stored in a selected one of said decoder registers.

Claim 21

Apparatus according to claim 17 wherein said decoder further includes means for inverting selected ones of said data signals received from said channel in response to a match between certain ones of said syndrome signals and signals generated by said decoder control means.