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US3699362A Expired / Lapsed US ⏱️ 0.0 years remaining

Transistor logic circuit

Assignee: International Business Machines Corp
•
Filing: 1971-05-27
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Granted: 1972-10-17
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Expires: 1991-05-27
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Abstract

Abstract A transistor-transistor logic circuit employing a Schottky barrier diode connected across the output of the multi-emitter input transistor and the reference potential to suppress transient overshoot by controlling the voltage at the collector of the input transistor of the TTL circuit.

Inventors

  • 👤 Paul V Jordan

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 22:13
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H03; H03K; H03K17/00; H03K17/16; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 143 words
In a logic circuit having a multi-emitter transistor input means for receiving input logic signals and responding by operating in either a first condition or a second condition, an output transistor means for providing an output logic signal, means connecting the collector of the input transistor means to the output transistor means and operable to bias the output transistor To a substantially non-conducting condition when the input transistor means is in a first operating condition and to a conducting condition when the input transistor means is in a second operating condition, the improvement comprising; a Schottky barrier diode connected to the collector of said input transistor means and a reference potential which operates to eliminate signal fluctuations from the collector of said input transistor means when in a first operating condition by controlling the voltage at the collector of the said input transistor.
Claim 2
Dependent Claim 143 words
In a logic circuit having a multi-emitter transistor input means for receiving input logic signals and responding by operating in either a first condition or a second condition, an output transistor means for providing an output logic signal, means connecting the collector of the input transistor means to the output transistor means and operable to bias the output transistor To a substantially non-conducting condition when the input transistor means is in a first operating condition and to a conducting condition when the input transistor means is in a second operating condition, the improvement comprising; a Schottky barrier diode connected to the collector of said input transistor means and a reference potential which operates to eliminate signal fluctuations from the collector of said input transistor means when in a first operating condition by controlling the voltage at the collector of the said input transistor.
Claim 3
Dependent Claim 53 words
The logic circuit of claim 1 wherein said multi-emitter transistor input means is a NPN transistor the cathode of said Schottky barrier diode connected to the collector of the said input transistor means and the anode connected to the reference potential, said reference potential being more negative than the emitter of said transistor.
Claim 4
Dependent Claim 63 words
The logic circuit of claim 1 embodied in an integrated semiconductor circuit device having the input transistor with a collector region extending to the top surface of the device, said Schottky diode comprising; a barrier layer located on the top surface of said collector region, a metallurgy stripe in electrical contact with said barrier layer and a region maintained at the reference potential.
Claim 5
Dependent Claim 33 words
The logic circuit of claim 3 wherein said region maintained at a reference potential is a diffused region of an impurity opposite the impurity in said collector region that encircles said input transistor.

References Cited (Backward Citations)

US3144563A Cited
US3089041A Cited
US3495141A Cited
US3555294A Cited
US3522444A Cited
US3614467A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-10-17 1976-04-17 1976-10-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-10-17 1980-04-17 1980-10-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-10-17 1984-04-17 1984-10-17 $7700.00 Window Closed / Lapsed

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