Gate circuit

Claim 2

A circuit comprising input means, output means, first semiconductor means having a conduction path and a control electrode for controlling conduction through said conduction path, said control electrode connected to said input means, and a first end of said conduction path connected to said output means to provide increased noise immunity of said circuit, second semiconductor means having a conduction path and a control electrode for controlling conduction through said conduction path, said control electrode connected to the first end of said conduction path of said first semiconductor means and said conduction path of said second semiconductor means connected to said output means to control said output means in accordance with the condition of said first semiconductor means, coupling means connected from said input means to said output means, said conduction path of said second semiconductor means connected to said coupling means to couple said input means to said output means as a function of the condition of said second semiconductor means, and feedback means connected from said output means to the second end of said conduction path of said first semi-conductor means, said feedback means selectively supplying a signal from said output means to said first semiconductor means for causing said first semiconductor means to control the operation of said output means.

Claim 3

The circuit recited in Claim 1 wherein said feedback means comprises third semiconductor means having a conduction path and a control electrode for controlling conduction in said conduction path, source means, said conduction path of said third semiconductor means connected between said source means and the second end of said conduction path of said first semiconductor means, and said control electrode of said third semiconductor means connected to said output means.

Claim 4

The circuit recited in claim 1 wherein said input means includes gating means including a third semiconductor means having a conduction path and a control electrode for controlling the conduction in said conduction path, source means connected to the control electrode, means for receiving a plurality of input signals connected to a first end of said conduction path, and means for coupling the second end of said conduction path to said first semiconductor means and said coupling means, said gating means producing a signal in accordance with the condition of said input signal, and clamp means connected to said gating means to supply predetermined signals thereto in the absence of input signals.

Claim 5

The combination comprising an input terminal, first and second circuit points, a first semiconductor means having first and second electrodes, and having a control electrode coupled to said input terminal, a second semiconductor means having a control electrode coupled to the first electrode of said first semiconductor means, a first electrode coupled to the first circuit point, and a second electrode coupled to the second circuit point, and a third semiconductor means having a control electrode coupled to the second electrode of said second semiconductor means, a first electrode coupled to the second electrode of said first semiconductor means, and a second electrode coupled to said second circuit point.

Claim 6

The combination comprising an input terminal, first and second circuit points, a first semiconductor means having first and second electrodes, and having a control electrode coupled to said input terminal, a second semiconductor means having a control electrode coupled to the first electrode of said first semiconductor means, a first electrode coupled to the first circuit point, and a second electrode coupled to the second circuit point, and a third semiconductor means having a control electrode coupled to the second electrode of said second semiconductor means, a first electrode coupled to the second electrode of said first semiconductor means, and a second electrode coupled to said second circuit point.

Claim 7

The combination claimed in claim 4 and further including resistive means connected between the first electrode of said first semiconductor means and said first circuit point, and an output terminal connected to the second electrode of said second semiconductor means.

Claim 8

The combination claimed in claim 4 wherein the first electrode of each of the first, second and third semiconductor means is an emitter electrode, and wherein the second electrode of each of said semiconductor means is a collector electrode.

Claim 9

The combination claimed in claim 4 including a fourth semiconductor means having a control electrode coupled to said input terminal and having first and second electrodes which define the ends of a conduction path through the fourth semiconductor means, wherein the coupling of the second electrode of said second semiconductor means to said second circuit point is by way of said conduction path.

Claim 10

In combination, a plurality of semiconductor devices each of which includes a conduction path having first and second terminals and a control terminal for controlling conduction through said conduction path, an input terminal, source means having first and second terminals, said input terminal connected to the control terminal of a first one of said semiconductor devices, the first terminal of said first semiconductor device connected to the control terminal of a second one of said semiconductor devices and to said first terminal of said source means, the second terminal of said first semiconductor device connected to the control terminal of a third one of said semiconductor devices and to said second terminal of said source means, the first terminal of said second semiconductor device connected to Said first terminal of said source means, the second terminal of said second semiconductor device connected to the first terminal of a fourth one of said semiconductor devices and to the control terminal of a fifth one of said semiconductor devices, the second terminal of said third semiconductor device connected to said second terminal of said source means and to the control terminal of a sixth one of said semiconductor devices, the control terminal of said fourth semiconductor device connected to the second terminal of said third semiconductor device, the second terminal of said fourth semiconductor device connected to said second terminal of said source means, the first terminal of said fifth semiconductor device connected to said first terminal of said source means, the second terminal of said fifth semiconductor device connected at a common junction with the fist terminal of said sixth semiconductor device, the second terminal of said sixth semiconductor device connected to said second terminal of said source means, the control terminal of a seventh one of said semiconductor devices connected to said common junction, the first terminal of said seventh semiconductor device connected to said first terminal of said source means, the second terminal of said seventh semiconductor device connected to the first terminal of said third semiconductor device, and an output terminal connected to said common junction.

Claim 11

In combination, a plurality of semiconductor devices each of which includes a conduction path having first and second terminals and a control terminal for controlling conduction through said conduction path, an input terminal, source means having first and second terminals, said input terminal connected to the control terminal of a first one of said semiconductor devices, the first terminal of said first semiconductor device connected to the control terminal of a second one of said semiconductor devices and to said first terminal of said source means, the second terminal of said first semiconductor device connected to the control terminal of a third one of said semiconductor devices and to said second terminal of said source means, the first terminal of said second semiconductor device connected to Said first terminal of said source means, the second terminal of said second semiconductor device connected to the first terminal of a fourth one of said semiconductor devices and to the control terminal of a fifth one of said semiconductor devices, the second terminal of said third semiconductor device connected to said second terminal of said source means and to the control terminal of a sixth one of said semiconductor devices, the control terminal of said fourth semiconductor device connected to the second terminal of said third semiconductor device, the second terminal of said fourth semiconductor device connected to said second terminal of said source means, the first terminal of said fifth semiconductor device connected to said first terminal of said source means, the second terminal of said fifth semiconductor device connected at a common junction with the fist terminal of said sixth semiconductor device, the second terminal of said sixth semiconductor device connected to said second terminal of said source means, the control terminal of a seventh one of said semiconductor devices connected to said common junction, the first terminal of said seventh semiconductor device connected to said first terminal of said source means, the second terminal of said seventh semiconductor device connected to the first terminal of said third semiconductor device, and an output terminal connected to said common junction.

Claim 12

The combination recited in claim 8 wherein each of said semiconductor devices comprises a transistor, said first and second terminals correspond to the collector and emitter electrodes of the respective transistors, and said control terminals correspond to the base electrodes of the respective transistors.

Claim 13

A circuit comprising input means, output means including a pair of semiconductor devices each having a conduction path and a control electrode for controlling the conduction in said conduction path, said conduction paths connected in series and defining an output terminal at the junction thereof, first semiconductor means connected between said input means and said control electrode of one of said semiconductor devices within said output means to provide increased noise immunity of said circuit, second semiconductor means connected from said first semiconductor means to said control electrode of said other semiconductor device within said output means to control said output means in accordance with the condition of said first semiconductor means, coupling means connected from said input means to said control electrode of said other semiconductor device within said output means and said second semiconductor means to couple said input means to said output means as a function of the condition of said second semiconductor means, and feedback means connected from said output means to said first semiconductor means, said feedback means selectively supplying a signal from said output means to said first semiconductor means for causing said first semiconductor means to control the operation of said output means.

Claim 14

A circuit comprising input means, output means including a pair of semiconductor devices each having a conduction path and a control electrode for controlling the conduction in said conduction path, said conduction paths connected in series and defining an output terminal at the junction thereof, first semiconductor means connected between said input means and said control electrode of one of said semiconductor devices within said output means to provide increased noise immunity of said circuit, second semiconductor means connected from said first semiconductor means to said control electrode of said other semiconductor device within said output means to control said output means in accordance with the condition of said first semiconductor means, coupling means connected from said input means to said control electrode of said other semiconductor device within said output means and said second semiconductor means to couple said input means to said output means as a function of the condition of said second semiconductor means, and feedback means connected from said output means to said first semiconductor means, said feedback means selectively supplying a signal from said output means to said first semiconductor means for causing said first semiconductor means to control the operation of said output means.

Claim 15

The circuit recited in claim 10 wherein said feedback means comprises third semiconductor means having a conduction path and a control electrode for controlling conduction in said conduction path, source means, said conduction path of said third semiconductor means connected between said source means and said first semiconductor means, and said control electrode of said third semiconductor means connected to said output terminal.

Claim 16

The circuit recited in claim 10 wherein said input means includes gating means including a third semiconductor means having a conduction path and a control electrode for controlling the conduction in said conduction path, source means connected to the control electrode, means for receiving a plurality of input signals connected to a first end of said conduction path, and means for coupling the second end of said conduction path to said first semiconductor means and said coupling means, said gating means producing a signal in accordance with the condition of said input signal, and clamp means connected to said gating means to supply predetermined signals thereto in the absence of input signals.

Claim 17

The circuit recited in claim 10 wherein said feedback means is connected from said output terminal to said first semiconductor means to transmit a signal representative of an output signal having a magnitude greater than a prescribed level to said first semiconductor means whereby said other semiconductor of said pair of semiconductor devices causes said output signal to assume a magnitude smaller than said prescribed level.