US3699273A
Expired / Lapsed
US
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Echo suppression gate for digital code words including noise insertion
Assignee: AT&T Inc
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Filing: 1970-12-24
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Granted: 1972-10-17
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Expires: 1990-12-24
Abstract
Abstract Apparatus for suppressing echoes in digital speech transmission systems includes a serial-to-parallel converter, a buffer store and a parallel-to-serial converter. Digital code words propagating in serial form are first converted to parallel code words. The bits of the parallel code words are then supplied to the buffer store. An echo is suppressed by clearing the buffer store of the stored bits of the digital code word representing the echo and supplying logical signals representing substantially a zero amplitude signal to the parallel-to-serial converter. During the suppression of an echo code word, noise is automatically inserted into the transmission facility by allowing the logical signal in at least the last bit of the code word being suppressed to pass unaltered.
Inventors
- 👤 William Lloyd Montgomery
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 13:42
CPC Classifications
H; H04; H04B; H04B3/00; H04B3/02; H04B3/20
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
100 words
A digital echo suppression gate which comprises, storage means, first means for supplying digital code words having a plurality of bits to said storage means, means for transmitting the bits of said code words, controllable means for transferring the bits of individual code words stored in said storage means to said transmitting means, said controllable means being responsive to inhibit the transfeR of said stored code word bits in accordance with a pre-established criterion, and second means for supplying digital signals having a predetermined logical state to said transmitting means when the transfer of said code word bits is inhibited.
Claim 2
Dependent Claim
100 words
A digital echo suppression gate which comprises, storage means, first means for supplying digital code words having a plurality of bits to said storage means, means for transmitting the bits of said code words, controllable means for transferring the bits of individual code words stored in said storage means to said transmitting means, said controllable means being responsive to inhibit the transfeR of said stored code word bits in accordance with a pre-established criterion, and second means for supplying digital signals having a predetermined logical state to said transmitting means when the transfer of said code word bits is inhibited.
Claim 3
Dependent Claim
47 words
A suppression gate as defined in claim 1 wherein said first supplying means includes means for converting serial code words having a plurality of bits into parallel code words and coupling means for controllably transferring said parallel code word bits to said storage means at predetermined instants.
Claim 4
Dependent Claim
58 words
An echo suppression gate as defined in claim 2 wherein said storage means has a plurality of stages, said serial-to-parallel converter means includes a first shift register having a plurality of stages, and said coupling means includes a plurality of AND gates, said AND gates being in a one-to-one circuit relationship with the stages of said storage means.
Claim 5
Dependent Claim
23 words
A suppression gate as defined in claim 1 wherein said transmitting means includes means for converting parallel code words to serial code words.
Claim 6
Dependent Claim
74 words
A suppression gate as defined in claim 4 wherein said storage means has a plurality of stages, said parallel-to-serial converter means includes a shift register having a plurality of stages, said controllable means includes a plurality of AND gates, said AND gates being in a one-to-one circuit relationship with individual stages of said storage means and individual stages of said shift register, and further including means for generating signals to control said AND gates.
Claim 7
Dependent Claim
77 words
A digital echo suppression gate which comprises, storage means, means for supplying digital code words having a plurality of bits to said storage means, means for substituting digital signals having a predetermined logical state for the bits of individual code words stored in said storage means in accordance with a pre-established criterion, and means for inhibiting the substitution of said predetermined digital signals for at least a selected one of the bits of said individual code words.
Claim 8
Dependent Claim
77 words
A digital echo suppression gate which comprises, storage means, means for supplying digital code words having a plurality of bits to said storage means, means for substituting digital signals having a predetermined logical state for the bits of individual code words stored in said storage means in accordance with a pre-established criterion, and means for inhibiting the substitution of said predetermined digital signals for at least a selected one of the bits of said individual code words.
Claim 9
Dependent Claim
161 words
A digital echo suppression gate which comprises, first shift register means having a plurality of stages, first means for supplying digital code words having a plurality of bits to the stages of said first shift register means, storage means having a plurality of stages, means for transferring the bits of said code words from the stages of said first shift register means to the stages of said storage means at predetermined instants, second shift register means having a plurality of stages, and controllable means for transferring the bits of individual ones of said code words from the stages of said storage means to the stages of said second shift register means, said controllable means including means for inhibiting the transfer of said code word bits to said second register means and second means for supplying digital signals having a predetermined logic state to the stages of said second shift register means when the transfer of said code word bits is inhibited.
Claim 10
Dependent Claim
161 words
A digital echo suppression gate which comprises, first shift register means having a plurality of stages, first means for supplying digital code words having a plurality of bits to the stages of said first shift register means, storage means having a plurality of stages, means for transferring the bits of said code words from the stages of said first shift register means to the stages of said storage means at predetermined instants, second shift register means having a plurality of stages, and controllable means for transferring the bits of individual ones of said code words from the stages of said storage means to the stages of said second shift register means, said controllable means including means for inhibiting the transfer of said code word bits to said second register means and second means for supplying digital signals having a predetermined logic state to the stages of said second shift register means when the transfer of said code word bits is inhibited.
Claim 11
Dependent Claim
33 words
A suppression gate as defined in claim 7 wherein said transferring means includes a plurality of AND gates, said AND gates being in a one-to-one relationship with the stages of said storage means.
Claim 12
Dependent Claim
57 words
An echo suppression gate as defined in claim 7 wherein said inhibiting means includes a plurality of AND gates, said AND gates being in a one-to-one circuit relationship with the stages of said second shift register means and the stages of said storage means, and means for generating signals at predetermined instants to control said AND gates.
Claim 13
Dependent Claim
82 words
A digital echo suppression gate as defined in claim 7 wherein said controllable means further includes means for allowing at least a selected one of the bits of said individual code words to transfer unaltered from said storage means to said second shift register means when the others of said bits are inhibited and wherein said second supplying means includes means for supplying digital signals having a predetermined logic state to said second shift register means for the others of said bits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-17 | 1976-04-17 | 1976-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-17 | 1980-04-17 | 1980-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-17 | 1984-04-17 | 1984-10-17 | $7700.00 | Window Closed / Lapsed |