Clock timing signal

Claim 1

A UNIPOLAR TO BIPOLAR PULSE CONVERTER COMPRISING, IN COMBINATION, A SOURCE OF UNIPOLAR PULSE INPUT SIGNALS WHICH GENERATES UNIPOLAR PULSES AND SPACES EACH OF WHICH OCCUPIES A PREDETERMINED TIME INTERVAL, A FIRST SOURCE OF PULSE TIMING SIGNALS WHICH GENERATES FIRST TIMING SIGNALS ONE OF WHICH OCCURS AT THE BEGINNING OF EACH PULSE TIME INTERVAL, A SECOND SOURCE OF PULSE TIMING SIGNALS WHICH GENERATES SECOND TIMING SIGNALS ONE OF WHICH OCCURS AT THE END OF EACH PULSE TIME INTERVAL, AND AND GATE TO WHICH SAID SOURCE OF UNIPOLAR PULSE INPUT SIGNALS AND SAID FIRST SOURCE OF TIMING SIGNALS ARE CONNECTED TO GENERATE AT AN OUTPUT TERMINAL AN OUTPUT CURRENT UPON THE OCCURRENCE AT THE SAME INSTANT OF TIME OF A UNIPOLAR INPUT PULSE AND A FIRST TIMING PULSE, A PAIR OF BLOCKING OSCILLATORS EACH OF WHICH GENERATES PULSES WHICH ARE OPPOSITE IN POLARITY, A FIRST UNILATERAL CURRENT CONDUCTIVE ELEMENT AND A FIRST CAPACITOR SERIALLY CONNECTED BETWEEN SAID OUTPUT TERMINAL OF SAID AND GATE AND THE FEEDBACK PATH OF A FIRST OF SAID BLOCKING OSCILLATORS, A SECOND UNILATERAL CURRENT CONDUCTIVE ELEMENT AND A SECOND CAPACITOR SERIALLY CONNECTED BETWEEN SAID OUTPUT TERMINAL OF SAID AND GATE AND THE FEEDBACK PATH OF A SECOND OF SAID BLOCKING OSCILLATORS, MEANS TO DISCHARGE SAID FIRST CAPACITOR AND DISCHARGE SAID SECOND CAPACITOR WHEN SAID FIRST BLOCKING OSCILLATOR IS GENERATING AN OUTPUT PULSE IN RESPONSE TO A FIRST OUTPUT CURRENT GENERATED BY SAID AND GATE, MEANS TO CHANGE SAID SECOND CAPACITOR AND DISCHARGE SAID FIRST CAPACITOR WHEN SAID SECOND BLOCKING OSCILLATOR IS GENERATING AN OUTPUT PULSE IN RESPONSE TO A SECOND OUTPUT CURRENT GENERATED BY SAID AND GATE, MEANS CONNECTED TO SAID SECOND SOURCE OF PULSE TIMING SIGNALS TO TERMINATE THE GENERATION OF AN OUTPUT PULSE BY SAID BLOCKING OSCILLATORS AT THE END OF A PULSE TIME INTERVAL, WHEREBY SAID BLOCKING OSCILLATORS ALTERNATE IN GENERATING OUTPUT PULSES IN RESPONSE TO INPUT PULSES FROM SAID SOURCE OF UNIPOLAR INPUT PULSES.