Patent US3697977A successfully refreshed from Google Patents.
US3697977A
Expired / Lapsed
US
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Two phase encoder system for three frequency modulation
Assignee: Honeywell Inc
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Filing: 1970-07-06
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Granted: 1972-10-10
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Expires: 1990-07-06
Abstract
Abstract A multiphase encoder translates the bits of a Non-Return-to-Zero digital signal into a three frequency self-clocking having a data transition at the center of a binary ONE bit and a data transition between successive binary ZERO bits.
Inventors
- 👤 George H Sollman
- 👤 Samuel J Dixon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:47
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4904; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
414 words
An encoder for translating bits of a NRZ data input signal into a self-clocking waveform comprising: a two phase clock for generating pulses of first and second phase signals having 180* out-of-phase relationship to one another in response to an input clock waveform; means for synchronizing the timing of said NRZ data signal with a predetermined phase signal of said clock so that the pulses of said first phase signal occur within the center of said bits and the pulses of said second phase signal occur at boundaries between bits; a first clocked flip-flop having a CLOCK input for receiving said pulses of said second phase signal and a DATA input for receiving said NRZ signal, said flip-flop being conditioned by pulses of said second phase signal and said NRZ signal to produce a first data signal and its complement, each delayed from said NRZ signal by one bit time; a second clocked flip-flop having a CLOCK input for receiving said pulses of said second phase signal and a DATA input, said flip-flop including gating means for receiving said complement of said first data signal and the complement of said NRZ signal and being connected to apply an output signal to said DATA input, said second flip-flop being conditioned by pulses of said second phase signal to generate a second data signal and its complement in accordance with said output signal corresponding to the sum of said first data signal and said NRZ signal; first gating means for receiving the complement of said second data signal and pulses of said second phase signal, said first gating means being conditioned to pass pulses of said second phase signal when said complement of said second data signal is in a state representative of the occurrence of successive ZERO bits in said NRZ signal; second gating means for receiving said first data signal and said pulses of said first phAse signal, said second gating means being conditioned to pass pulses of said first phase signal when said first data signal is in a state representative of the occurrence of a binary ONE bit in said NRZ signal; third gating means coupled to first and second gating means; and, complementing bistable means coupled to said third gating means and being conditioned by said pulses of said first and second phase signals to produce as an output said self-clocking waveform having transitions at the center of a binary ONE bit and at the boundaries between successive binary ZERO bits.
Claim 2
Dependent Claim
414 words
An encoder for translating bits of a NRZ data input signal into a self-clocking waveform comprising: a two phase clock for generating pulses of first and second phase signals having 180* out-of-phase relationship to one another in response to an input clock waveform; means for synchronizing the timing of said NRZ data signal with a predetermined phase signal of said clock so that the pulses of said first phase signal occur within the center of said bits and the pulses of said second phase signal occur at boundaries between bits; a first clocked flip-flop having a CLOCK input for receiving said pulses of said second phase signal and a DATA input for receiving said NRZ signal, said flip-flop being conditioned by pulses of said second phase signal and said NRZ signal to produce a first data signal and its complement, each delayed from said NRZ signal by one bit time; a second clocked flip-flop having a CLOCK input for receiving said pulses of said second phase signal and a DATA input, said flip-flop including gating means for receiving said complement of said first data signal and the complement of said NRZ signal and being connected to apply an output signal to said DATA input, said second flip-flop being conditioned by pulses of said second phase signal to generate a second data signal and its complement in accordance with said output signal corresponding to the sum of said first data signal and said NRZ signal; first gating means for receiving the complement of said second data signal and pulses of said second phase signal, said first gating means being conditioned to pass pulses of said second phase signal when said complement of said second data signal is in a state representative of the occurrence of successive ZERO bits in said NRZ signal; second gating means for receiving said first data signal and said pulses of said first phAse signal, said second gating means being conditioned to pass pulses of said first phase signal when said first data signal is in a state representative of the occurrence of a binary ONE bit in said NRZ signal; third gating means coupled to first and second gating means; and, complementing bistable means coupled to said third gating means and being conditioned by said pulses of said first and second phase signals to produce as an output said self-clocking waveform having transitions at the center of a binary ONE bit and at the boundaries between successive binary ZERO bits.
Claim 3
Dependent Claim
13 words
The encoder of claim 1 wherein said flip-flops are of the D type.
Claim 4
Dependent Claim
12 words
The encoder of claim 1 wherein said gating means are NAND gates.
Claim 5
Dependent Claim
64 words
The encoder of claim 1 wherein said synchronizing means includes a data shift register connected to receive said pulses of said second phase signal and said register being conditioned by said pulses to apply the bits of said NRZ signal to said first flip-flop so as to establish a predetermined phase relationship between said bits and the pulses of each of said phase signals.
Claim 6
Dependent Claim
88 words
The encoder of claim 1 wherein said two phase clock includes a complementing bistable storage device connected to receive said input clock waveform and being operative in response to said input clock waveform to generate a pair of complementary outputs; first and second gates, each gate being coupled to receive said clock waveform and a different one of said complementary outputs, said first and second gates respectively being conditioned by said clock waveform and said different one of said outputs to generate said first and second phase signals.
Claim 7
Dependent Claim
20 words
The encoder of claim 5 wherein said bistable device is a D type flip-flop and said gates are NAND gates.
Claim 8
Dependent Claim
395 words
An encoder for translating the bits of a NRZ data waveform into a self clocking three frequency waveform using a first phase signal having pulses which occur only at the center of the bit intervals of said NRZ waveform and a second phase signal having pulses which occur only at the boundaries of said bit intervals, said encoder comprising: a first clocked bistable storage device and a second clocked bistable storage device, each of said devices having a CLOCK input for receiving pulses of said second signal, and a DATA input for receiving an input data waveform, each clocked device being conditioned by said pulses of said second phase signal to produce a pair of complementary outputs, each pair of outputs being delayed by one bit interval relative to said input data waveform, the DATA input of said first bistable storage device being connected to receive said NRZ waveform as said input data waveform and said second storage device including input gating means connected to receive a predetermined one of the outputs of said first storage device and the complement of said NRZ waveform and being operative to apply as an output said input data waveform to the DATA input of said second bistable device storage; first gating means for receiving a predetermined one of the outputs of said second bistable device and pulses of said second phase signal, said first gating means being conditioned to pass pulses of said second phase signal when said predetermined one of said outputs is in a state representative of the occurrence of successive ZERO bits in said NRZ waveform; second gating means for receiving the other of said outputs of said first bistable storage device and the pulses of said first phase signal, said gating means being conditioned to pass pulses of said first phase signal when said other output is in a state representative of the occurrence of a binary ONE bit in said NRZ waveform; third gating means coupled to said first and second gating means for receiving pulses of said first and second phase signals; and, a complementing output flip-flop coupled to said third gating means and being conditioned by said pulses of said first and second phase signals to Produce said self-clocking three frequency waveform having transitions at the center of each binary ONE bit and at the boundaries between successive binary ZERO bits.
Claim 9
Dependent Claim
395 words
An encoder for translating the bits of a NRZ data waveform into a self clocking three frequency waveform using a first phase signal having pulses which occur only at the center of the bit intervals of said NRZ waveform and a second phase signal having pulses which occur only at the boundaries of said bit intervals, said encoder comprising: a first clocked bistable storage device and a second clocked bistable storage device, each of said devices having a CLOCK input for receiving pulses of said second signal, and a DATA input for receiving an input data waveform, each clocked device being conditioned by said pulses of said second phase signal to produce a pair of complementary outputs, each pair of outputs being delayed by one bit interval relative to said input data waveform, the DATA input of said first bistable storage device being connected to receive said NRZ waveform as said input data waveform and said second storage device including input gating means connected to receive a predetermined one of the outputs of said first storage device and the complement of said NRZ waveform and being operative to apply as an output said input data waveform to the DATA input of said second bistable device storage; first gating means for receiving a predetermined one of the outputs of said second bistable device and pulses of said second phase signal, said first gating means being conditioned to pass pulses of said second phase signal when said predetermined one of said outputs is in a state representative of the occurrence of successive ZERO bits in said NRZ waveform; second gating means for receiving the other of said outputs of said first bistable storage device and the pulses of said first phase signal, said gating means being conditioned to pass pulses of said first phase signal when said other output is in a state representative of the occurrence of a binary ONE bit in said NRZ waveform; third gating means coupled to said first and second gating means for receiving pulses of said first and second phase signals; and, a complementing output flip-flop coupled to said third gating means and being conditioned by said pulses of said first and second phase signals to Produce said self-clocking three frequency waveform having transitions at the center of each binary ONE bit and at the boundaries between successive binary ZERO bits.
Claim 10
Dependent Claim
14 words
The encoder of claim 7 wherein said bistable storage devices are D type flip-flops.
Claim 11
Dependent Claim
14 words
The encoder of claim 7 wherein each of said gating means include NAND gates.
Claim 12
Dependent Claim
362 words
An improved encoder for translating bits of a data stream waveform W into a self-clocking waveform comprising: a two phase clock generator for generating pulses of first and second phases phi 1 and phi 2 in response to a clock input signal so as to have the phi 1 pulses coincide with the centers of said bits and the phi 2 pulses coincide with the boundaries of said bits; a first clocked flip-flop including a CLOCK input for receiving said phi 2 pulses and a DATA input for receiving said data waveform W, said first flip-flop being conditioned by said phi 2 pulses, to switch state in accordance with said waveform W to produce a waveform W1 and its complement, W1, each delayed by a bit interval relative to said waveform W; a first gate connected to receive the complement waveform W1 and the complement of said waveform W, said first gate being enabled to produce a data signal in accordance with the expression: W1 + W; a second clocked flip-flop including a CLOCK input for receiving said phi 2 pulses and a DATA input for receiving said data signal, said second flip-flop being conditioned by said phi 2 pulses to switch state in accordance with said data signal to produce a waveform F1 whose state represents the occurrence of two adjacent ZERO bits in said waveform W; a second gate connected to receive said waveform F1 and said phi 2 pulses, said gate being enabled to produce a pulse output F2 defined by the relationship: F2 F1. phi 2; a third gate connected to receive said complement waveform W1 and said phi 1 pulses, said gate being enabled to produce a pulse output F3 defined by the relationship: F3 W1. phi 1; and, a complementing output flip-flop including a gate connected to said second and third gates, said gate being arranged to apply a complementing pulse signal F4 in accordance with the expression: F4 F2+F3, said flip-flop being conditioned by said signal F4 to switch state during a bit interval of said data stream waveform W when there is a ONE and between bit intervals when there are two successive ZEROS.
Claim 13
Dependent Claim
362 words
An improved encoder for translating bits of a data stream waveform W into a self-clocking waveform comprising: a two phase clock generator for generating pulses of first and second phases phi 1 and phi 2 in response to a clock input signal so as to have the phi 1 pulses coincide with the centers of said bits and the phi 2 pulses coincide with the boundaries of said bits; a first clocked flip-flop including a CLOCK input for receiving said phi 2 pulses and a DATA input for receiving said data waveform W, said first flip-flop being conditioned by said phi 2 pulses, to switch state in accordance with said waveform W to produce a waveform W1 and its complement, W1, each delayed by a bit interval relative to said waveform W; a first gate connected to receive the complement waveform W1 and the complement of said waveform W, said first gate being enabled to produce a data signal in accordance with the expression: W1 + W; a second clocked flip-flop including a CLOCK input for receiving said phi 2 pulses and a DATA input for receiving said data signal, said second flip-flop being conditioned by said phi 2 pulses to switch state in accordance with said data signal to produce a waveform F1 whose state represents the occurrence of two adjacent ZERO bits in said waveform W; a second gate connected to receive said waveform F1 and said phi 2 pulses, said gate being enabled to produce a pulse output F2 defined by the relationship: F2 F1. phi 2; a third gate connected to receive said complement waveform W1 and said phi 1 pulses, said gate being enabled to produce a pulse output F3 defined by the relationship: F3 W1. phi 1; and, a complementing output flip-flop including a gate connected to said second and third gates, said gate being arranged to apply a complementing pulse signal F4 in accordance with the expression: F4 F2+F3, said flip-flop being conditioned by said signal F4 to switch state during a bit interval of said data stream waveform W when there is a ONE and between bit intervals when there are two successive ZEROS.
Claim 14
Dependent Claim
13 words
The encoder of claim 10 wherein said flip-flops are of the D type.
Claim 15
Dependent Claim
30 words
The encoder of claim 10 wherein said gates are NAND gates and said complementing output flip-flop is arranged to switch state at the trailing edge of said pulse signal F4.
Claim 16
Dependent Claim
54 words
The encoder of claim 10 further including a data shift register connected to receive said phi 2 pulses and being conditioned to apply the bits of said data waveform to said DATA input of said first flip-flop so as to establish the relationship between said bits and said phi 1 and phi 2 pulses.
Claim 17
Dependent Claim
62 words
The encoder of claim 10 wherein said two phase clock generator includes a complementing flip-flop connected to generate a pair of complementing outputs from said clock input and first and second gates connected to receive said clock input and a different one of said complementing outputs, said first and second gates being conditioned to generate said phi 1 and phi 2 pulses.
Claim 18
Dependent Claim
19 words
The encoder of claim 14 wherein said flip-flop is of the D type and said gates are NAND gates.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-10 | 1976-04-10 | 1976-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-10 | 1980-04-10 | 1980-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-10 | 1984-04-10 | 1984-10-10 | $7700.00 | Window Closed / Lapsed |