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US3697784A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuits
Assignee: US Philips Corp
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Filing: 1971-02-04
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Granted: 1972-10-10
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Expires: 1991-02-04
Abstract
Abstract An integrated circuit eliminates the feedback effect of spurious signals between a push-pull transistor pair in separate islands and a third transistor in a third island by locating the third transistor island at a null point of the electric field pattern in the substrate corresponding to a spurious signal originating from the push-pull transistors.
Inventors
- 👤 Kenneth William Moulding
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:34
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/189; H03F3/19; H03F3/195; H10; H10D; H10D89/00; H10D89/10
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
137 words
A semiconductor integrated circuit comprising a common semiconductor substrate, at least three circuit elements in said substrate, isolation means bounding each of said circuit elements, means connecting two of said circuit elements as a push-pull pair, and means to couple the third of said circuit elements to said push-pull pair whereby said push-pull pair is an output stage for said third circuit element, spurious signals passing from said two circuit elements in said push-pull pair over a path including region-to-substrate capacitance of said two circuit elements and the bulk conduction of said substrate establishing in said substrate an electric potential pattern including at least one null point, said third circuit element being located at a null of the electric potential pattern in order to substantially eliminate in the substrate any undesired feedback effects of the spurious signals.
Claim 2
Dependent Claim
137 words
A semiconductor integrated circuit comprising a common semiconductor substrate, at least three circuit elements in said substrate, isolation means bounding each of said circuit elements, means connecting two of said circuit elements as a push-pull pair, and means to couple the third of said circuit elements to said push-pull pair whereby said push-pull pair is an output stage for said third circuit element, spurious signals passing from said two circuit elements in said push-pull pair over a path including region-to-substrate capacitance of said two circuit elements and the bulk conduction of said substrate establishing in said substrate an electric potential pattern including at least one null point, said third circuit element being located at a null of the electric potential pattern in order to substantially eliminate in the substrate any undesired feedback effects of the spurious signals.
Claim 3
Dependent Claim
24 words
A semiconductor integrated circuit as claimed in claim 1, wherein said circuit elements are transistors, each of said transistors being formed in an island.
Claim 4
Dependent Claim
26 words
A semiconductor integrated circuit as claimed in claim 1, wherein said third circuit element is symmetrically located with respect to said first and second circuit elements.
Claim 5
Dependent Claim
133 words
A semiconductor integrated circuit comprising a common semiconductor substrate, at least three circuit elements in said substrate, isolation means bounding each of said circuit elements, means connecting two of said circuit elements as a push-pull pair, and means to couple said push-pull pair to the third of said circuit element whereby said circuit elements is an output stage for said push-pull pair, spurious signals passing from said third circuit element to said two circuit elements over paths including region-to-substrate capacitance of said two circuit elements and the bulk conduction of said substrate establishing in said substrate an electric potential pattern including two equipotential points, each of said two circuit elements being located at two equipotential points respectively in order to eliminate substantially in said substate any undesired feedback effects of the spurious signals.
Claim 6
Dependent Claim
133 words
A semiconductor integrated circuit comprising a common semiconductor substrate, at least three circuit elements in said substrate, isolation means bounding each of said circuit elements, means connecting two of said circuit elements as a push-pull pair, and means to couple said push-pull pair to the third of said circuit element whereby said circuit elements is an output stage for said push-pull pair, spurious signals passing from said third circuit element to said two circuit elements over paths including region-to-substrate capacitance of said two circuit elements and the bulk conduction of said substrate establishing in said substrate an electric potential pattern including two equipotential points, each of said two circuit elements being located at two equipotential points respectively in order to eliminate substantially in said substate any undesired feedback effects of the spurious signals.
Claim 7
Dependent Claim
24 words
A semiconductor integrated circuit as claimed in claim 4, wherein said circuit element are transistors, each of said transistors being formed in an island.
Claim 8
Dependent Claim
26 words
A semiconductor integrated circuit as claimed in claim 4, wherein said third circuit element is symmetrically located with respect to said first and second circuit elements.
Claim 9
Dependent Claim
40 words
A semiconductor integrated circuit as claimed in claim 3, wherein the semiconductor body comprises a fourth island, a fourth transistor being provided in said fourth island, said fourth island being located symmetrically with respect to the first and second islands.
Claim 10
Dependent Claim
41 words
A semiconductor integrated circuit as claimed in claim 7, wherein the transistor of said third and fourth islands are connected in push-pull and form an input stage for the push-pull pair formed by the transistors of said first and second islands.
Claim 11
Dependent Claim
31 words
A semiconductor integrated circuit as claimed in claim 6, wherein the semiconductor body comprises a fourth island, a fourth island being locateD symmetrically with respect to the first and second islands.
Claim 12
Dependent Claim
41 words
A semiconductor integrated circuit as claimed in claim 9, wherein the transistor of said third and fourth islands are connected in push-pull and form an input stage for the push-pull pair formed by the transistors of said first and second islands.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-10 | 1976-04-10 | 1976-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-10 | 1980-04-10 | 1980-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-10 | 1984-04-10 | 1984-10-10 | $7700.00 | Window Closed / Lapsed |