Patent US3697690A successfully refreshed from Google Patents.
US3697690A
Expired / Lapsed
US
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Dual-mode phase-locked loop with dead zone phase detector
Assignee: AT&T Inc
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Filing: 1971-06-29
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Granted: 1972-10-10
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Expires: 1991-06-29
Abstract
Abstract A timing circuit generates the timing signal used in the regeneration of a pulse code modulation signal which contains a timing burst between each word. This is accomplished by synchronizing a voltage-controlled oscillator (VCO) to the timing burst with a dual-mode phase-locked loop. One loop contains a phase detector with a dead zone, which compares the VCO output with a burst detector signal. This phase detector produces an error signal only until the frequencies of the two signals are the same and their phases are within a prescribed range of each other. The other loop contains a gated phase detector which compares the VCO output to the timing burst and produces a second error signal which is combined with the first to control the VCO.
Inventors
- 👤 Marvin Robert Aaron
- 👤 Warren Gail Hammett
- 👤 James Francis Oberst
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 15:21
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/08; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/087; H03L7/10; H03L7/107; H03L7/1075
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
251 words
A timing extraction circuit for synchronizing an oscillator having a pulsed output to an input signal, said input signal being characterized by timing frequency burst which are spaced periodically in said input signal, comprising: a burst detection means for generating a burst detection signal at its output on the occurrence of a frequency burst in the input signal; a voltage-controlled oscillator having a control terminal and an output terminal; a frequency dividing means connected to the output of said voltage-controlled oscillator, which passes one of every n pulses from said voltage-controlled oscillator; a first phase detecting means having a first input connected to the output of said frequency dividing means and a second input connected to the output of said burst detection means, which compares the output of said frequency dividing means with the burst detection signal and produces a first error signal at its output which is related to the comparison; a second phase detecting means having a first input connected to the output of said voltage-controlled oscillator, a second input connected to receive the input signal, and a third input connected to the output of said burst detection means, which compares the output of said voltage-controlled oscillator to the frequency burst in the input signal, whenever the burst detection signal is present, and produces a second error signal at its output which is related in the comparison; and a means for combining the first and second error signals and applying them to the control terminal of said voltagecontrolled oscillator.
Claim 2
Dependent Claim
251 words
A timing extraction circuit for synchronizing an oscillator having a pulsed output to an input signal, said input signal being characterized by timing frequency burst which are spaced periodically in said input signal, comprising: a burst detection means for generating a burst detection signal at its output on the occurrence of a frequency burst in the input signal; a voltage-controlled oscillator having a control terminal and an output terminal; a frequency dividing means connected to the output of said voltage-controlled oscillator, which passes one of every n pulses from said voltage-controlled oscillator; a first phase detecting means having a first input connected to the output of said frequency dividing means and a second input connected to the output of said burst detection means, which compares the output of said frequency dividing means with the burst detection signal and produces a first error signal at its output which is related to the comparison; a second phase detecting means having a first input connected to the output of said voltage-controlled oscillator, a second input connected to receive the input signal, and a third input connected to the output of said burst detection means, which compares the output of said voltage-controlled oscillator to the frequency burst in the input signal, whenever the burst detection signal is present, and produces a second error signal at its output which is related in the comparison; and a means for combining the first and second error signals and applying them to the control terminal of said voltagecontrolled oscillator.
Claim 3
Dependent Claim
62 words
A circuit as claimed in claim 1 wherein said first phase detecting means comprises a dead-zone phase detector which compares the output of said frequency dividing means with the burst detection signal and produces the first error signal which is present only until the frequencies of the two signals are substantially the same and their relative phases are within a prescribed limit.
Claim 4
Dependent Claim
81 words
A circuit as claimed in claim 1 wherein said means for combining the first and second error signals comprises: a first filter connected to the output of said first phase detecting means; a second filter connected to the output of said second phase detecting means; a summing amplifier which sums the output signals of said first filter and said second filter; and a third filter connected between the output of said summing amplifier and the control terminal of said voltage-controlled oscillator.
Claim 5
Dependent Claim
328 words
A timing extraction circuit for synchronizing an oscillator having a pulsed output to an input signal, said input signal being characterized by timing frequency bursts which are spaced periodically in said input signal, comprising: a burst detection means for generating a burst detection signal at its output of the occurrence of a frequency burst in the output signal; a voltage-controlled oscillator having a control terminal and an output terminal; a frequency dividing means connected to the output of said voltage-controlled oscillator, which passes one of every n pulses from said voltage-controlled oscillator; a variable time delay means having a control terminal, an output terminal, and input terminal which is connected to the output of said frequency dividing means, said variable time delay means varying the phase of the pulses from said frequency dividing means in response to a signal on its control terminal; a first phase detecting means having a first input connected to the output of said variable time delay means and a second input connected to the output of said burst detection means, which compares the output of said variable time delay means with the burst detection signal and produces a first error signal at its output which is related to the comparison; a first filter means connected between the output of said first phase detecting means and the control terminal of said voltage-controlled oscillator; a second phase detecting means having a first input connected to the output of said voltage-controlled oscillator, a second input connected to said input signal, and a third input connected to the output of said burst detection means, which compares the output of said voltage-controlled oscillator to the frequency burst in the input signal, whenever the burst detection signal is present, and produces a second error signal at its output which is related to the comparison; and a second filtering means connected between the output of said second phase detecting means and the control terminal of said variable time delay means.
Claim 6
Dependent Claim
328 words
A timing extraction circuit for synchronizing an oscillator having a pulsed output to an input signal, said input signal being characterized by timing frequency bursts which are spaced periodically in said input signal, comprising: a burst detection means for generating a burst detection signal at its output of the occurrence of a frequency burst in the output signal; a voltage-controlled oscillator having a control terminal and an output terminal; a frequency dividing means connected to the output of said voltage-controlled oscillator, which passes one of every n pulses from said voltage-controlled oscillator; a variable time delay means having a control terminal, an output terminal, and input terminal which is connected to the output of said frequency dividing means, said variable time delay means varying the phase of the pulses from said frequency dividing means in response to a signal on its control terminal; a first phase detecting means having a first input connected to the output of said variable time delay means and a second input connected to the output of said burst detection means, which compares the output of said variable time delay means with the burst detection signal and produces a first error signal at its output which is related to the comparison; a first filter means connected between the output of said first phase detecting means and the control terminal of said voltage-controlled oscillator; a second phase detecting means having a first input connected to the output of said voltage-controlled oscillator, a second input connected to said input signal, and a third input connected to the output of said burst detection means, which compares the output of said voltage-controlled oscillator to the frequency burst in the input signal, whenever the burst detection signal is present, and produces a second error signal at its output which is related to the comparison; and a second filtering means connected between the output of said second phase detecting means and the control terminal of said variable time delay means.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-10 | 1976-04-10 | 1976-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-10 | 1980-04-10 | 1980-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-10 | 1984-04-10 | 1984-10-10 | $7700.00 | Window Closed / Lapsed |