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US3696402A
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Digital frequency divider
Assignee: Bull HN Information Systems Italia SpA
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Filing: 1970-11-23
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Granted: 1972-10-03
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Expires: 1990-11-23
Abstract
Abstract Digital pulse rates are divided by storing sequential bit groups, each of which has a number of bits equal to the factor by which the rate is to be divided, and generating an output pulse for each group. Each output pulse is equal to the majority binary value in that group. Where each group has an even number of bits, a toggle is used to establish the output value for groups where no majority value exists.
Inventors
- 👤 Thomas R Armstrong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:39
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30; H03K; H03K23/00; H03K23/64; H03K23/66; H03K23/667
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
188 words
A digital frequency compressor for dividing the rate of data comprising, first storage means for storing the values of successive binary digits, second storage means connected to said storage means for storing the value in said first storage means upon occurrence of a successive digit, third storage means for storing a third value, logic means responsive to said first, second and third storage means for producing an output value representing a majority of the binary values in said first, second and third storage means, whereby said majority value is a true majority of the binary values in said first and second storage means when there is a predominant binary value in said first and second storage means, and whereby said majority value is a random majority of the binary values in said first, second and third storage means when there is no predominant binary value in said first and second storage means, and output means coupled to said logic means for selecting the outputs of said logic means and maintaining them for periods equal in bit intervals to the number by which the data are to be divided.
Claim 2
Dependent Claim
188 words
A digital frequency compressor for dividing the rate of data comprising, first storage means for storing the values of successive binary digits, second storage means connected to said storage means for storing the value in said first storage means upon occurrence of a successive digit, third storage means for storing a third value, logic means responsive to said first, second and third storage means for producing an output value representing a majority of the binary values in said first, second and third storage means, whereby said majority value is a true majority of the binary values in said first and second storage means when there is a predominant binary value in said first and second storage means, and whereby said majority value is a random majority of the binary values in said first, second and third storage means when there is no predominant binary value in said first and second storage means, and output means coupled to said logic means for selecting the outputs of said logic means and maintaining them for periods equal in bit intervals to the number by which the data are to be divided.
Claim 3
Dependent Claim
163 words
A digital frequency compressor for dividing the rate of data comprising, first storage means for storing the values of successive binary digits, second storage means connected to said first storage means for storing the value in said first storage means upon occurrence of a successive digit, third storage means for storing a third value, logic means responsiVe to said first, second and third storage means for producing an output value representing a majority of the binary values in said first, second and third storage means said logic means having the Boolean equation R TB1 + TB2 + B1B2 where B1 is the output of said first storage means B2 is the output of said second storage means and T is the output of said third storage means, and output means coupled to said logic means for selecting the outputs of said logic means and maintaining them for periods equal in bit intervals to the number by which the data are to be divided.
Claim 4
Dependent Claim
163 words
A digital frequency compressor for dividing the rate of data comprising, first storage means for storing the values of successive binary digits, second storage means connected to said first storage means for storing the value in said first storage means upon occurrence of a successive digit, third storage means for storing a third value, logic means responsiVe to said first, second and third storage means for producing an output value representing a majority of the binary values in said first, second and third storage means said logic means having the Boolean equation R TB1 + TB2 + B1B2 where B1 is the output of said first storage means B2 is the output of said second storage means and T is the output of said third storage means, and output means coupled to said logic means for selecting the outputs of said logic means and maintaining them for periods equal in bit intervals to the number by which the data are to be divided.
Claim 5
Dependent Claim
44 words
An apparatus as in claim 1, further comprising clock means synchronous with said data bits, and wherein said third storage means include frequency divider means responsive to said clock means for producing an output at a fraction of the rate of said clock means.
Claim 6
Dependent Claim
40 words
An apparatus as in claim 1, wherein said logic means produce sequential outputs representing the majority binary value in said storage means at any one time, and said output means select one of the sequential outputs of said logic means.
Claim 7
Dependent Claim
25 words
A device as in claim 4 wherein said divider means comprises a flip-flop and produces an output at half the rate of said clock means.
Claim 8
Independent Claim
136 words
A system for transmitting analog information comprising analog-to-digital converter means for converting the analog information to digital information, a plurality of storage means coupled to said converter means for shifting the digital information to a plurality of consecutive positions, logic means coupled to said storage means for producing an output value that represents a majority of the values in said plurality of storage means, output means responsive to said logic means for establishing an output signal corresponding to the outputs of said logic means and maintaining them for equal time increments that are each a multiple of a bit in the digital information, channel means coupled to said output means for transmitting the output of said output means, and digital-to-analog converter means coupled to said channel means for demodulating the signals passing through said channel means.
Claim 9
Independent Claim
136 words
A system for transmitting analog information comprising analog-to-digital converter means for converting the analog information to digital information, a plurality of storage means coupled to said converter means for shifting the digital information to a plurality of consecutive positions, logic means coupled to said storage means for producing an output value that represents a majority of the values in said plurality of storage means, output means responsive to said logic means for establishing an output signal corresponding to the outputs of said logic means and maintaining them for equal time increments that are each a multiple of a bit in the digital information, channel means coupled to said output means for transmitting the output of said output means, and digital-to-analog converter means coupled to said channel means for demodulating the signals passing through said channel means.
Claim 10
Dependent Claim
25 words
A system as in claim 6 wherein said output means establish an output signal corresponding to selected ONES of the outputs of said logic means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-03 | 1976-04-03 | 1976-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-03 | 1980-04-03 | 1980-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-03 | 1984-04-03 | 1984-10-03 | $7700.00 | Window Closed / Lapsed |