Data storage system with means for eliminating defective storage locations

Claim 2

In a data storage system in which a very large number of identical memory elements are combined into an integrated memory matrix in such a manner that words of a given number of bits are stored, and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: additional memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable memory elements being modified in such a manner that it causes a distinctive signal to be emitted when it is interrogated, which identifies the unusability thereof; means for interrogating all the said memory elements of a word; and means responsive to said distinctive signals emitted during interrogation and operative during the writing in said memory matrix of a word, for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element and each of the succeeding bits of the word to the next-following bit locations of the word containing usable memory elements whereby the bits of the word are stored in said memory matrix in their proper sequence.

Claim 3

A data storage system as defined in claim 1 wherein said means responsive to the signal emitted during interrogation include means operative during the reading out of words from said memory matrix for shifting the data bits of the word read from said memory matrix to suppress those bit locations which belong to unusable memory elements.

Claim 4

A data storage system as defined in claim 2 wherein at least one auxiliary loop is provided for a series logic circuit train of said system to reduce the travel time of the data therethrough, said auxiliary loop bridges at least some of the logic circuit members and containing a circuit element having a unidirectional signal transmitting direction, said circuit element being in said loop in such a manner that the forward direction of the auxiliary loop coincides with the forward direction of the signal.

Claim 5

A data storage system as defined in claim 3 wherein said circuit element is a diode or a transistor.

Claim 6

A data storage system as defined in claim 3 wherein said circuit element comprises an already available logic circuit which is further utilized as a portion of said auxiliary loop.

Claim 7

A data storage system as defined in claim 3 wherein the output of each of the logic circuit members in said series chain is connected, by means of auxiliary loops, with the inputs of each subsequent logic circuit member in the forward direction, via one of said circuit elements.

Claim 8

A data storage system as defined in claim 3 wherein the output of each of the logic circuit members in consecutive segments of said chain of logic circuit members is connected through auxiliary loops with the inputs of each subsequent logic circuit member of the same segment in the forward direction via a said circuit element, and wherein an appropriate connection technique is employed with reference to the beginning and eNd points of the individual segments.

Claim 9

In a data storage system in which a very large number of identical memory elements are combined into an integrated memory matrix in such a manner that words of a given number of bits are stored, and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: additional memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable memory elements being modified in such a manner that it causes a distinctive signal to be emitted when it is interrogated, which identifies the unusability thereof; means for interrogating all the said memory elements of a word; and means responsive to said distinctive signals emitted during interrogation and (a) operative during the writing of a word into said memory matrix for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element to the next-following bit location of the word containing usable memory element and (b) further operative during the reading out of words from said memory matrix for shifting the data bits of the word read from said memory matrix to suppress those bit locations which belong to unusable memory elements, said means responsive to said distinctive signals including: at least a first shift register having a number of binary stages equal to the number of the given bits plus the number of the additional memory elements provided for each word, said first shift register being responsive to said distinctive signals so that those stages corresponding to the bit locations of the unusable memory elements are in a first binary condition and the remaining stages are in the opposite binary condition; a further shift register having the same number of binary stages as said first shift register, said further shift register being coupled to said memory and containing the word to be written in or read out from said memory; and logic circuit means interconnecting said first and further shift registers and responsive to the condition of the stages of said first shift register for shifting the data bits within said further shift register in a timed pattern in a first direction during the write-in operation until the data bits are located in the respective stages of said further shift register corresponding to bit locations having only usable memory elements, and in the opposite direction during the readout operation until all of the data bits are in adjacent stages of said further shift register, said logic circuit means being responsive to the condition of the first stage of said first shift register which is in said first condition to shift only the data bits in the subsequent corresponding stages of said further shift register.

Claim 10

In a data storage system in which a very large number of identical memory elements are combined into an integrated memory matrix in such a manner that words of a given number of bits are stored, and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: additional memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable memory elements being modified in such a manner that it causes a distinctive signal to be emitted when it is interrogated, which identifies the unusability thereof; means for interrogating all the said memory elements of a word; and means responsive to said distinctive signals emitted during interrogation and (a) operative during the writing of a word into said memory matrix for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element to the next-following bit location of the word containing usable memory element and (b) further operative during the reading out of words from said memory matrix for shifting the data bits of the word read from said memory matrix to suppress those bit locations which belong to unusable memory elements, said means responsive to said distinctive signals including: at least a first shift register having a number of binary stages equal to the number of the given bits plus the number of the additional memory elements provided for each word, said first shift register being responsive to said distinctive signals so that those stages corresponding to the bit locations of the unusable memory elements are in a first binary condition and the remaining stages are in the opposite binary condition; a further shift register having the same number of binary stages as said first shift register, said further shift register being coupled to said memory and containing the word to be written in or read out from said memory; and logic circuit means interconnecting said first and further shift registers and responsive to the condition of the stages of said first shift register for shifting the data bits within said further shift register in a timed pattern in a first direction during the write-in operation until the data bits are located in the respective stages of said further shift register corresponding to bit locations having only usable memory elements, and in the opposite direction during the readout operation until all of the data bits are in adjacent stages of said further shift register, said logic circuit means being responsive to the condition of the first stage of said first shift register which is in said first condition to shift only the data bits in the subsequent corresponding stages of said further shift register.

Claim 11

A data storage system as defined in claim 8 including means responsive to the signals emitted by the memory elements of a word during interrogation for preventing the initiation of the sequence of logical operations performed by said means for shifting the data bits when said distinctive signals indicate that unusable memory elements are not contained within the word being read, whereby the travel time of the data during readout is reduced.

Claim 12

A data storage system as defined in claim 9 wherein said means for preventing the said logical sequence of operations comprises an interrogation circuit means connected to the stages of said first shift register for producing an output signal whenever at least one stage of said first shift register is in said first condition, the absence of said output signal from said interrogation circuit means initiating the evaluation of the unchanged contents of said further shift register.

Claim 13

A data storage system as defined in claIm 10 wherein said interrogation circuit means is an OR circuit.

Claim 14

In a data storage system in which a very large number of identical memory elements are combined into an integrated memory matrix in such a manner that words of a given number of bits are stored, and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: additional memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable memory elements being modified in such a manner that it causes a distinctive signal to be emitted when it is interrogated, which identifies the unusability thereof; means for interrogating all the said memory elements of a word; and means responsive to said distinctive signals emitted during interrogation and (a) operative during the writing of a word into said memory matrix for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element to the next-following bit location of the word containing usable memory element, and (b) further operative during the reading out of words from said memory matrix for shifting the data bits of the word read from said memory matrix to suppress those bit locations which belong to unusable memory elements, said means responsive to said distinctive signals including: at least a first shift register having a number of binary stages equal to the number of the given bits plus the number of additional memory elements provided for each word, said first shift register being responsive to said distinctive signals so that those stages corresponding to the bit locations of unusable memory elements are in a first binary condition and the remaining stages are in the opposite binary condition; a further shift register having the same number of stages as said first shift register, said further shift register being coupled to said memory and containing the word to be written in or read out from said memory; means for parallelly writing in or reading out the bits of a data word from said further shift register including a plurality of selector switch means equal in number to the number of bits in the word, with each of said selector switch means having a number of switching positions which is greater by one than the number of said additional memory elements, each of said switch means being coupled to the stages of said further shift register to switch through, depending on its switching position, the directly associated stage of said further shift register or the next-higher locations thereof, and means responsive to the contents of said first shift register for determining the switching position of said selector switch means so that the bit locations in said memory containing unusable memory elements are eliminated.

Claim 15

In a data storage system in which a very large number of identical memory elements are combined into an integrated memory matrix in such a manner that words of a given number of bits are stored, and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: additional memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable memory elements being modified in such a manner that it causes a distinctive signal to be emitted when it is interrogated, which identifies the unusability thereof; means for interrogating all the said memory elements of a word; and means responsive to said distinctive signals emitted during interrogation and (a) operative during the writing of a word into said memory matrix for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element to the next-following bit location of the word containing usable memory element, and (b) further operative during the reading out of words from said memory matrix for shifting the data bits of the word read from said memory matrix to suppress those bit locations which belong to unusable memory elements, said means responsive to said distinctive signals including: at least a first shift register having a number of binary stages equal to the number of the given bits plus the number of additional memory elements provided for each word, said first shift register being responsive to said distinctive signals so that those stages corresponding to the bit locations of unusable memory elements are in a first binary condition and the remaining stages are in the opposite binary condition; a further shift register having the same number of stages as said first shift register, said further shift register being coupled to said memory and containing the word to be written in or read out from said memory; means for parallelly writing in or reading out the bits of a data word from said further shift register including a plurality of selector switch means equal in number to the number of bits in the word, with each of said selector switch means having a number of switching positions which is greater by one than the number of said additional memory elements, each of said switch means being coupled to the stages of said further shift register to switch through, depending on its switching position, the directly associated stage of said further shift register or the next-higher locations thereof, and means responsive to the contents of said first shift register for determining the switching position of said selector switch means so that the bit locations in said memory containing unusable memory elements are eliminated.

Claim 16

A data storage system as defined in claim 12 wherein said means for determining the switching position of each of said selector switch means comprises a logic network means which is associated with said first shift register for emitting a ''''first shift order'''' by first switching all of the stages of said first shift register after the first stage which is in said first binary condition to said first binary condition and then switching said first stage of said first shift register which is in said first binary condition to the opposite binary condition; said logic network correspondingly utilizing the thus changed information to derive further ''''shift orders'''' until the maximum permissible number of error data contained in the stages in said first condition has been switched to the opposite binary condition.

Claim 17

In a data storage system in which a very large number of identical bistable flipflop memory elements are combined inTo an integrated memory matrix in such a manner that words of a given number of bits are stored, and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: additional bistable flipflop memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable memory elements being disconnected from at least one of the word and bit lines associated with the unusable memory element in such a manner that during readout a distinctive output signal results at the unusable memory element which differs in its amplitude from the output signals of the usable memory elements and thus identifies the unusability thereof; means for interrogating all the said memory elements of a word; and means responsive to said distinctive signals emitted during readout and operative during the writing of a word into said memory matrix, for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element to the next-following bit location of the word containing a usable memory element.

Claim 18

In a data storage system in which a very large number of identical bistable flipflop memory elements are combined inTo an integrated memory matrix in such a manner that words of a given number of bits are stored, and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: additional bistable flipflop memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable memory elements being disconnected from at least one of the word and bit lines associated with the unusable memory element in such a manner that during readout a distinctive output signal results at the unusable memory element which differs in its amplitude from the output signals of the usable memory elements and thus identifies the unusability thereof; means for interrogating all the said memory elements of a word; and means responsive to said distinctive signals emitted during readout and operative during the writing of a word into said memory matrix, for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element to the next-following bit location of the word containing a usable memory element.

Claim 19

A data storage system as defined in claim 14 wherein, all of said bistable flipflops are connected to at least one of the word and bit lines of said memory via a fuse element, and wherein the fuse elements of the unusable memory elements are burned out, thereby separating the unusable memory element from the associated line, by passing a current of sufficient magnitude through said associated line.

Claim 20

A data storage system as defined in claim 15 wherein each of said memory elements is provided with a diode connected in series with said fuse element, the associated bit or word line and an auxiliary line through which current is fed via said diodes to burn out the fuse elements of the unusable memory elements, and means for applying a voltage to said auxiliary lines to maintain the said diodes of the usable memory elements in a blocked condition.

Claim 21

A data storage system as defined in claim 14, wherein the identification of the unusable memory elements is accomplished by providing the said means for interrogating the memory elements with means for producing a special potential, which differs from the potentials emitted by a usable memory element in its two possible memory states, when the unusable memory element is interrogated via the bit readout line.

Claim 22

A data storage system as defined in claim 17 wherein said special potential differs from the potential present on the bit lines in the rest state.

Claim 23

A data storage system as defined in claim 17 wherein said special potential coincides with the potential on said bit lines in the rest state, and wherein said means for interrogating said memory elements causes the potentials produced on the bit line by a usable memory element in either of its two possible storage states when being interrogated to be different from the potential present on the bit line when the memory is in the rest state.

Claim 24

A data storage system as defined in claim 14 wherein the two complementary outputs of said flipflops are connected to bit lines with the identical outputs of all of the usable memory elements in any bit location being connected in groups with a single readout line, and wherein outputs of the unusable memory elements are not connected with a readout line.

Claim 25

A data storage system as defined in claim 20 wherein one of the two signals which can be emitted by each output of a usable memory element coincides with the rest potential in the readout line.

Claim 26

In a data storage system in which a very large number of identical thin film ferromagnetic memory elements are combined into an integrated memory matrix in such a manner that words of a given number of bits are storEd, and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: additional thin film ferromagnetic memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable elements being modified by the destruction of its magnetic characteristic by the application of strong heat, preferably with the aid of laser beams, so that it causes a distinctive signal to be emitted when it is interrogated, which identifies the unusability thereof; means for interrogating all the said memory elements of a word; and means responsive to said distinctive signals emitted during interrogation and (a) operative during the writing of a word into said memory matrix for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element to the next-following bit location of the word containing a usable memory element, and (b) further operative during the reading out of words from said memory matrix for shifting the data bits of the word read from said memory matrix to suppress those bit locations which belong to unusable memory elements.

Claim 27

In a data storage system in which a very large number of identical thin film ferromagnetic memory elements are combined into an integrated memory matrix in such a manner that words of a given number of bits are storEd, and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: additional thin film ferromagnetic memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable elements being modified by the destruction of its magnetic characteristic by the application of strong heat, preferably with the aid of laser beams, so that it causes a distinctive signal to be emitted when it is interrogated, which identifies the unusability thereof; means for interrogating all the said memory elements of a word; and means responsive to said distinctive signals emitted during interrogation and (a) operative during the writing of a word into said memory matrix for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element to the next-following bit location of the word containing a usable memory element, and (b) further operative during the reading out of words from said memory matrix for shifting the data bits of the word read from said memory matrix to suppress those bit locations which belong to unusable memory elements.

Claim 28

In a data storage system in which a very large number of identical memory elements are combined into an integrated memory matrix in such a manner that words of a given number of bits are stored, and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: said memory matrix being constructed such that each word has two associated spatially separated addresses within the memory which are connected in parallel; additional memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable memory elements being modified in such a manner that it causes a distinctive signal to be emitted when it is interrogated, which identifies the unusability thereof; means for interrogating all the said memory elements of a word; and means responsive to said distinctive signals emitted during interrogation and (a) operative during the writing of a word into said memory matrix for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element to the next-following bit location of the word containing a usable memory element, and (b) further operative during the reading out of words from said memory matrix for shifting the data bits of the word read from said memory matrix to suppress those bit locations which belong to unusable memory elements.

Claim 29

In a data storage system in which a very large number of identical memory elements are combined into an integrated memory matrix in such a manner that words of a given number of bits are stored, and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: said memory matrix being constructed such that each word has two associated spatially separated addresses within the memory which are connected in parallel; additional memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable memory elements being modified in such a manner that it causes a distinctive signal to be emitted when it is interrogated, which identifies the unusability thereof; means for interrogating all the said memory elements of a word; and means responsive to said distinctive signals emitted during interrogation and (a) operative during the writing of a word into said memory matrix for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element to the next-following bit location of the word containing a usable memory element, and (b) further operative during the reading out of words from said memory matrix for shifting the data bits of the word read from said memory matrix to suppress those bit locations which belong to unusable memory elements.

Claim 30

In a data storage system in which a very large number of identical memory elements are combined into an integrated memory matrix in such a manner that words of a given number of bits are stored, said memory matrix being the main memory of said data storage system and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: additional memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable memory elements being modified in such a manner that it causes a distinctive signal to be emitted when it is interrogated, which identifies the unusability thereof; means for interrogating all the said memoRy elements of a word; means responsive to said distinctive signals emitted during interrogation and (a) operative during the writing of a word into said memory matrix for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element to the next-following bit location of the word containing a usable memory element and (b) further operative during the reading out of words from said memory matrix for shifting the data bits of the word read from said memory matrix to suppress those bit locations which belong to unusable memory elements a separate auxiliary memory for storing those data words which can not be written into a particular word address in said main memory; circuit means interconnecting said main and auxiliary memories for simultaneously reading out the associated information from said auxiliary memory when said particular word address in said main memory is addressed; and priority circuit means connected to the outputs of said main and auxiliary memories for passing only the output signals from said auxiliary memory whenever output signals simultaneously appear at the output signals of both said main and auxiliary memories.

Claim 31

In a data storage system in which a very large number of identical memory elements are combined into an integrated memory matrix in such a manner that words of a given number of bits are stored, said memory matrix being the main memory of said data storage system and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: additional memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable memory elements being modified in such a manner that it causes a distinctive signal to be emitted when it is interrogated, which identifies the unusability thereof; means for interrogating all the said memoRy elements of a word; means responsive to said distinctive signals emitted during interrogation and (a) operative during the writing of a word into said memory matrix for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element to the next-following bit location of the word containing a usable memory element and (b) further operative during the reading out of words from said memory matrix for shifting the data bits of the word read from said memory matrix to suppress those bit locations which belong to unusable memory elements a separate auxiliary memory for storing those data words which can not be written into a particular word address in said main memory; circuit means interconnecting said main and auxiliary memories for simultaneously reading out the associated information from said auxiliary memory when said particular word address in said main memory is addressed; and priority circuit means connected to the outputs of said main and auxiliary memories for passing only the output signals from said auxiliary memory whenever output signals simultaneously appear at the output signals of both said main and auxiliary memories.

Claim 32

In a data storage system in which a very large number of identical memory elements are combined into an integrated memory matrix in such a manner that words of a given number of bits are stored, and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: additional memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable memory elements being modified in such a manner that it causes a distinctive signal to be emitted when it is interrogated, which identifies the unusability thereof; means for interrogating all the said memory elements of a word; means responsive to said distinctive signals emitted during interrogation and (a) operative during the writing of a word into said memory matrix for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element to the next-following bit location of the word containing a usable memory element, and (b) further operative during the reading out of words from said memory matrix for shifting the data bits of the word read from said memory matrix to suppress those bit locations which belong to unusable memory elements; said memory matrix being additionally used as an associative memory, and wherein for its use as an associative memory, additional wiring for the associative searching process is provided for said memory elements, said additional wiring being different for each particular system and is such that the unusable memory elements are bypassed and each bit or read line is connected to the same number of usable memory elements in said memory matrix.

Claim 33

In a data storage system in which a very large number of identical memory elements are combined into an integrated memory matrix in such a manner that words of a given number of bits are stored, and wherein, due to the manufacturing process employed, a portion of the memory elements in said memory matrix are normally unusable, the improvement comprising: additional memory elements in excess of the given number of bits being provided in said memory matrix for each word, with the number of said additional memory elements being selected to correspond with the number of unusable memory elements to be expected for said word as a result of the manufacturing process, each of said unusable memory elements being modified in such a manner that it causes a distinctive signal to be emitted when it is interrogated, which identifies the unusability thereof; means for interrogating all the said memory elements of a word; means responsive to said distinctive signals emitted during interrogation and (a) operative during the writing of a word into said memory matrix for shifting those bits of the word which are to be stored in a bit location containing an unusable memory element to the next-following bit location of the word containing a usable memory element, and (b) further operative during the reading out of words from said memory matrix for shifting the data bits of the word read from said memory matrix to suppress those bit locations which belong to unusable memory elements; said memory matrix being additionally used as an associative memory, and wherein for its use as an associative memory, additional wiring for the associative searching process is provided for said memory elements, said additional wiring being different for each particular system and is such that the unusable memory elements are bypassed and each bit or read line is connected to the same number of usable memory elements in said memory matrix.

Claim 34

A data storage system as defined in claim 25 wherein said additional wiring is in the form of an additional conductive plane produced by vapor deposition on said memory matrix.

Claim 35

A data storage system as defined in claim 26 wherein said additional conductive plane is additionally provided with connecting lines which short-circuit portions of said unusable memory elements so that they can now be identified upon interrogation.