Patent US3693152A successfully refreshed from Google Patents.
US3693152A
Expired / Lapsed
US
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Error detection circuit for decoders
Assignee: International Business Machines Corp
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Filing: 1970-12-21
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Granted: 1972-09-19
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Expires: 1990-12-21
Abstract
Abstract A decoder error detection circuit having a first and second OR circuit. The first OR circuit having as inputs thereto the half of the outputs from the decoder which represent binary numbers having the same parity. The inputs to the second OR circuit are obtained from the other half of the decoder outputs which represent binary numbers of the opposite parity of those in the first half. The output of the first and second OR circuits is connected to a logic circuit consisting of a NOR circuit and an AND circuit connected to each of said first and second OR circuits in parallel. The outputs of the NOR and AND circuits are OR''ed together to provide an error indication for any single hardware failure in the decoder being checked.
Inventors
- 👤 Se J Hong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:27
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/085
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
264 words
A detection circuit for errors caused by a single hardware failure in a decoder having n inputs and 2n outputs comprising: a first circuit having 2n/2 inputs and one output, each input connected to a respective one of the outputs of said decoder representing a binary number having the same parity; a second circuit having 2n/2 inputs and one output, each input connected to a respective one of the outputs of said decoder representing a binary number having the same parity but opposite to the parity represented by the outputs of said decoder connected to said first circuit; a logic circuit connected to the outputs of said first and second circuits for comparing the signals at said outputs of said first and second circuits to produce a single output signal indicating a failure in said decoder; said first and second circuits producing an output signal when one or more inputs thereto are energized, respectively, an output signal on one of the outputs from said first and seconD circuits representing an error free operation of said decoder, while the absence of an output signal from both said first and second circuits represents one type of failure in said decoder and the presence of an output signal at an output of both said first and second circuits represents another type of failure in said decoder, the connecting of the inputs of the first and second circuits to outputs of said decoder representing opposite parities, respectively, insures that said another type of failure in said decoder causes an output signal from both said first and second circuits.
Claim 2
Dependent Claim
264 words
A detection circuit for errors caused by a single hardware failure in a decoder having n inputs and 2n outputs comprising: a first circuit having 2n/2 inputs and one output, each input connected to a respective one of the outputs of said decoder representing a binary number having the same parity; a second circuit having 2n/2 inputs and one output, each input connected to a respective one of the outputs of said decoder representing a binary number having the same parity but opposite to the parity represented by the outputs of said decoder connected to said first circuit; a logic circuit connected to the outputs of said first and second circuits for comparing the signals at said outputs of said first and second circuits to produce a single output signal indicating a failure in said decoder; said first and second circuits producing an output signal when one or more inputs thereto are energized, respectively, an output signal on one of the outputs from said first and seconD circuits representing an error free operation of said decoder, while the absence of an output signal from both said first and second circuits represents one type of failure in said decoder and the presence of an output signal at an output of both said first and second circuits represents another type of failure in said decoder, the connecting of the inputs of the first and second circuits to outputs of said decoder representing opposite parities, respectively, insures that said another type of failure in said decoder causes an output signal from both said first and second circuits.
Claim 3
Dependent Claim
32 words
A detection circuit in accordance with claim 1, wherein said first and second circuits are OR circuits for producing an output signal when one or more of the inputs thereto are energized.
Claim 4
Dependent Claim
57 words
A detection circuit in accordance with claim 2, wherein said first OR circuit has its inputs connected to the half of the outputs of the decoder representing binary numbers having even parity and said second OR circuit has its inputs connected to the other half of the outputs of the decoder representing binary numbers having odd parity.
Claim 5
Dependent Claim
102 words
A detection circuit in accordance with claim 3, wherein said logic circuit comprises a NOR circuit having the output from each of said first and second OR circuits connected thereto as inputs and producing an output when the inputs thereto are both 0, and an AND circuit having the output from each of said first and second OR circuits connected thereto as inputs producing an output when the inputs thereto are both 1''s and a third OR circuit having an input from both said NOR circuit and said AND circuit for producing an output representing any single fault condition in said decoder.
References Cited (Backward Citations)
US3428945A
Cited
US3541507A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-19 | 1976-03-20 | 1976-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-19 | 1980-03-20 | 1980-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-19 | 1984-03-20 | 1984-09-19 | $7700.00 | Window Closed / Lapsed |