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US3693048A Expired / Lapsed US ⏱️ 0.0 years remaining

Fail open semiconductors

Assignee: Motors Liquidation Co
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Filing: 1970-10-19
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Granted: 1972-09-19
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Expires: 1990-10-19
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Abstract

Abstract A circuit element which includes a fusible device and a semiconductor device series-connected in an integral casing. When a power supply passes a current larger than a predetermined value through the fusible device, fusion takes place in the fusible device so as to prevent the current from changing the semiconductor device into a short circuit across the power supply. In a second embodiment the circuit element also includes a switch that is opened in response to heating of the semiconductor device above a certain temperature. The switch is seriesconnected with the fusible device and the semiconductor device so as to disable the circuit element until the semiconductor device temperature is below the certain temperature. The circuit element of the second embodiment also includes a lamp for indicating when the fusible device has fused and the semiconductor device has become a short circuit.

Inventors

  • 👤 Kenneth W Doversberger
  • 👤 Thomas J Furnival

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 20:08
CPC Classifications
H; H01; H01H; H01H85/00; H01H85/02; H01H85/0241

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 210 words
A semiconductor unit comprising in combination; a semiconductor element having spaced substantially parallel faces between which current flow takes place in normal use and at least one semiconductor junction therebetween, the element being subject to failure to a short circuit state when its power rating is exceeded; a pair of spaced imperforate plates of conducting material complementary to and substantially coextensive with one of said faces, one of said plates being in abutting relation to said one face; a thin plate of electrically insulating material complementary to and substantially coextensive with said spaced plate and intimately sandwiched between said spaced plates; a pair of terminals seated against the other of said faces and the other of said spaced plates, the terminals being substantially coextensive in area with the faces and spaced discs to hold the element and the plates sandwiched therebetween, a plurality of fusible conducting ribbons extending between said spaced plates respectively, and located outboard the same and at peripherally spaced positions thereabout, the cross-section of said ribbons being such that they fuse and interrupt the circuit between the terminals when current flow indicative of semiconductor failure occurs, and a casing secured to the terminals to enclose and maintain the integrity of the assembly of the element and plates.
Claim 2
Dependent Claim 210 words
A semiconductor unit comprising in combination; a semiconductor element having spaced substantially parallel faces between which current flow takes place in normal use and at least one semiconductor junction therebetween, the element being subject to failure to a short circuit state when its power rating is exceeded; a pair of spaced imperforate plates of conducting material complementary to and substantially coextensive with one of said faces, one of said plates being in abutting relation to said one face; a thin plate of electrically insulating material complementary to and substantially coextensive with said spaced plate and intimately sandwiched between said spaced plates; a pair of terminals seated against the other of said faces and the other of said spaced plates, the terminals being substantially coextensive in area with the faces and spaced discs to hold the element and the plates sandwiched therebetween, a plurality of fusible conducting ribbons extending between said spaced plates respectively, and located outboard the same and at peripherally spaced positions thereabout, the cross-section of said ribbons being such that they fuse and interrupt the circuit between the terminals when current flow indicative of semiconductor failure occurs, and a casing secured to the terminals to enclose and maintain the integrity of the assembly of the element and plates.

References Cited (Backward Citations)

US943698A Cited
US1738113A Cited
GB896996A Cited
US3027502A Cited
US3240908A Cited
US3164702A Cited
US3486155A Cited
US3558989A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-09-19 1976-03-20 1976-09-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-09-19 1980-03-20 1980-09-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-09-19 1984-03-20 1984-09-19 $7700.00 Window Closed / Lapsed

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