Time delay circuits

Claim 1

A time delay circuit hAving input and output terminals, comprising: a transistor having base, emitter and collector electrodes with said base electrode coupled to said input terminal; means coupled to said input terminal for applying a trigger input to the base electrode of said transistor to render said transistor conducting; a timing network having its input coupled to said collector electrode; circuit means connected between said output terminal and the output of said timing network and operable to assume one state in which a high potential appears at said output terminal and a second state in which a low potential appears at said output terminal in response to the output of said timing network, said circuit means including high gain transistorized amp lifting means for providing high impedance to said timing network and a sharp transition between said first and second states, feedback transistor means coupled about said amplifying means compensating for operating imbalance of said amplifying means, diode means coupled to said amplifying means for providing the thermal stabilization of said amplifying means, and further transistor means coupled to said amplifying means for rendering said circuit means substantially insensitive to changes in operating potentials applied to said circuit means; means for applying operating potentials to said transistor electrodes and to said circuit means; and means for coupling said output terminal to said transistor base electrode for maintaining said transistor conducting for a period determined substantially by said timing network.