Circuit arrangement for telecommunication switching systems employing time-division multiplex operation

Claim 2

A circuit arrangement for telecommunication switching systems for time-division multiplex switching of coded signals in fourwire operation via coordinate switching matrices made up of electronic switching elements, comprising a switching matrix, a plurality of inlets to the matrix, a plurality of control lines for reception of coded control signals for cross points in a column in said matrix, a first plurality of NAND-circuits responsive to signals from the inlets and the control lines, outputs of a row of said NAND-circuits respectively connected to the inputs of a further NAND-circuit whose output corresponds to a matrix outlet, and blocking devices arranged in said control lines which, if the control inlets are not wired, connect biasing potential to the respective inputs of said NAND-circuits.

Claim 3

A circuit arrangement according to claim 1, in which said blocking devices in said control lines for preventing the unintentional through-switching when the control inlets are not wired are resistors connecting biasing potential to each control inlet, thus keeping it blocked when it is not wired.

Claim 4

A circuit arrangement according to claim 1, in which the input impedance of said blocking device is equal to the characteristic impedance of said control line.

Claim 5

A circuit arrangement according to claim 1, in which said blocking devices in said control lines for preventing the unintentional through-switching when the control inlets are not wired are differential amplifiers which unblock one of the two inverse output control lines connected to said first NANd-circuits only if a potential difference between inverse control inlets appears while blocking both output control lines when the control inlets are not wired and, consequently, there is no potential difference at the inlet.

Claim 6

A circuit arrangement according to claim 1, in which said blocking devices for preventing the unintentional through-switching in single-conductor control lines are designed as differential amplifiers grounded at one terminal which, when a blocking signal is applied, block only the respective output control line while blocking both output control lines when the inlet is not wired.

Claim 7

A circuit arrangement according to claim 1, in which said control lines are grounded via diodes in order to keep any negative voltage peaks away from said switching elements.

Claim 8

A circuit arrangement according to claim 6, in which interference due to positive excess voltages is prevented by means of diodes.

Claim 9

A circuit arrangement according to claim 4, in which ECL gates are used as blocking devices.

Claim 10

A circuit arrangement for telecommunication switching systems for time-division multiplex switching of coded signals in four-wire operation via coordinate switching matrices made up of electronic switching elements, comprising a switching matrix, a plurality of inlets to the matrix, a plurality of control lines for reception of coded control signals for cross points in a column in said matrix, a first plurality of GATE-circuits responsive to signals from the inlets and the control lines, outputs of a row of said GATE-circuits respectively connected to the inputs of a further GATE-circuit whose output corresponds to a matrix outlet, and blocking devices arranged in said control lines which, if the control inlets are not wired, connect biasing potential to the respective inputs of said GATE-circuits.

Claim 11

A circuit arrangement for telecommunication switching systems for time-division multiplex switching of coded signals in four-wire operation via coordinate switching matrices made up of electronic switching elements, comprising a switching matrix, a plurality of inlets to the matrix, a plurality of control lines for reception of coded control signals for cross points in a column in said matrix, a first plurality of GATE-circuits responsive to signals from the inlets and the control lines, outputs of a row of said GATE-circuits respectively connected to the inputs of a further GATE-circuit whose output corresponds to a matrix outlet, and blocking devices arranged in said control lines which, if the control inlets are not wired, connect biasing potential to the respective inputs of said GATE-circuits.