Marker controlled electronic crosspoint

Claim 2

An electronic crosspoint for use in a switching system wherein connections are selectively enabled through a crosspoint in response to marking signals on an associated select lead and on an associated hold lead, wherein said electronic crosspoint comprises: an output gate for controlling data through said electronic crosspoint; electronic gate means responsive to the application of said marking signals on said select lead and on said hold lead for enabling said output gate; and means for inhibiting said enabling of said output gate when said hold signal is applied to said electronic gate means prior to said application of said select signal.

Claim 3

The invention set forth in claim 1, further comprising means exclusively controlled by said hold lead marking signal for maintaining said enabled output gate in said enabled condition.

Claim 4

The invention set forth in claim 2, wherein said electronic gate means comprises: a plurality of NAND gates each having an output controlled by two inputs and wherein: said inhibiting means includes means for generating a signal inverse to said hold lead marking signal and for comparing said inverse signal to said select lead marking signal.

Claim 5

The invention set forth in claim 2, wherein said electronic gate means comprises: a plurality of NOR gates each having an output controlled by two inputs and wherein: said inhibiting means includes means for generating a signal inverse to said select lead marking signal and for comparing said inverse signal to said hold lead marking signal.

Claim 6

An electronic crosspoint matrix for use in a common control switching system wherein connections may be enabled between a selected vertical multiple and a selected horizontal multiple through a crossbar switch in response to marking signals on one out of a plurality of select leads and on one out of a plurality of hold leads, said matrix operating in parallel with or as a substitute for said crossbar switch and including a plurality of electronic crosspoints, each said crosspoint comprising: an output gate for controlling data through said crosspoint; electronic gate means responsive to the receipt of said marking signals on an associated select lead and on an associated hold lead for enabling said output gate; means controlled exclusively by said hold lead marking signal for maintaining an enabled output gate in said enabled condition; and means for inhibiting said enabling of said output gate when said hold signal is received by said electronic gate means prior to said receipt of said select signal by said electronic gate means.

Claim 7

An electronic crosspoint matrix for use in a common control switching system wherein connections may be enabled between a selected vertical multiple and a selected horizontal multiple through a crossbar switch in response to marking signals on one out of a plurality of select leads and on one out of a plurality of hold leads, said matrix operating in parallel with or as a substitute for said crossbar switch and including a plurality of electronic crosspoints, each said crosspoint comprising: an output gate for controlling data through said crosspoint; electronic gate means responsive to the receipt of said marking signals on an associated select lead and on an associated hold lead for enabling said output gate; means controlled exclusively by said hold lead marking signal for maintaining an enabled output gate in said enabled condition; and means for inhibiting said enabling of said output gate when said hold signal is received by said electronic gate means prior to said receipt of said select signal by said electronic gate means.

Claim 8

The invention set forth in claim 5, wherein said output gate includes: a first input connected to an associated horizontal multiple; a second input connected to said electronic gate means; an output connected to an associated vertical multiple; and means jointly responsive to an enabling signal on said second input from said electronic gate means and to an enabling signal on said first input from said horizontal multiple for repeating said horizontal multiple signal on said associated vertical multiple.

Claim 9

A telephone switching system crosspoint comprising: an output gate for selectively controlling data through the crosspoint; a select input and a hold input for receiving enabling signals; a plurality of electronic gates each having a first and a second input and a single output, said gates being arranged iN a first and a second group, each of said groups having a primary gate, a memory gate, and a control gate, and wherein each of said groups includes: a connection between said output of said primary gate and said first input of said control gate; a connection between said output of said memory gate and said second input of said control gate; and a connection between said output of said control gate and said first input of said memory gate; said select input connected to said second input of said memory gate and connected to said first input of said primary gate in said first group of gates; said hold input connected to said second input of said primary gate in said first group of gates and connected to said second input of said primary gate and to said first input of said memory gate in said second group of gates; and interconnecting means between said first and said second groups of said gates and between said second group of said gates and said selectively controllable output gate, whereby said output gate is enabled in response to the receipt of an enabling signal on said select input followed by the receipt of an enabling signal on said hold input and said output gate is inhibited when said enabling signals are received in reverse order.

Claim 10

A telephone switching system crosspoint comprising: an output gate for selectively controlling data through the crosspoint; a select input and a hold input for receiving enabling signals; a plurality of electronic gates each having a first and a second input and a single output, said gates being arranged iN a first and a second group, each of said groups having a primary gate, a memory gate, and a control gate, and wherein each of said groups includes: a connection between said output of said primary gate and said first input of said control gate; a connection between said output of said memory gate and said second input of said control gate; and a connection between said output of said control gate and said first input of said memory gate; said select input connected to said second input of said memory gate and connected to said first input of said primary gate in said first group of gates; said hold input connected to said second input of said primary gate in said first group of gates and connected to said second input of said primary gate and to said first input of said memory gate in said second group of gates; and interconnecting means between said first and said second groups of said gates and between said second group of said gates and said selectively controllable output gate, whereby said output gate is enabled in response to the receipt of an enabling signal on said select input followed by the receipt of an enabling signal on said hold input and said output gate is inhibited when said enabling signals are received in reverse order.

Claim 11

The invention set forth in claim 7, wherein said electronic gates comprise a plurality of NAND gates and wherein said inhibiting means includes means for inverting said hold input signal and for comparing said select signal to said inverting signal.

Claim 12

The invention set forth in claim 8, further comprising means for maintaining an enabled output gate in said enabled condition under exclusive control of said hold input signal.

Claim 13

The invention set forth in claim 7, wherein said electronic gates comprise a plurality of NOR gates and wherein said inhibiting means includes means for inverting said select input signal and for comparing said inverted select signal to said hold input signal.

Claim 14

The invention set forth in claim 10, wherein said enabling means includes means for inverting said hold input signal; and means for maintaining the enabled output gate in said enabled condition under exclusive control of said inverted hold input signal.