Convertible nand/nor gate

Claim 2

A logic element for use in digital data processing comprising: input means for receiving a plurality of binary signals; controllable circuit means coupled to said input means for applying a result of a logic NAND operation, performed on said binary signals, to an output terminal in response to a first command signal and for applying a result of a logic NOR operation, performed on said binary signals, to said output terminal in response to a second command signal; and command input means, coupled to said circuit means for receiving control signals, said command input means producing said first command signal and said second command signal in response to said control signals.

Claim 3

The logic element of claim 1 wherein said circuit means comprises: a plurality of main transistors of the field effect type, each of said main transistors having a command electrode coupled to said input means; and a plurality of auxiliary transistors of the field effect type, each of said auxiliary transistors having a command electrode coupled to said command input means for receiving said first and said second command signals to enable said auxiliary transistors in response to said second command signal, and to disable said auxiliary transistors in response to said first command signal.

Claim 4

An integrated circuit element including transistors of a field effect type fabricated according to a metal-oxide-semiconductor technique comprising: at least a first main transistor, a second main transistor and a third main transistor, wherein command terminals of said main transistors receive binary logic signals, and wherein said first main transistor has a first source/drain electrode coupled to an output terminal, a second source/drain electrode of said first main transistor is coupled to a first source/drain electrode of said second main transistor, a second source/drain electrode of said second main transistor is coupled to a first source/drain electrode of said third transistor and a second source/drain electrode is coupled to a ground terminal; and at least a first auxiliary transistor and a second auxiliary transistor, wherein command electrodes of said auxiliary transistors receive control signals, wherein a first source/drain electrode of said first auxiliary transistor is coupled to said ground terminal and a second source/drain electrode is coupled to said second source/drain electrode of said first main transistor, and wherein a first source/drain electrode of said second auxiliary transistor is coupled to said output terminal while said second source/drain electrode of said second auxiliary transistor is coupled to said first source/drain electrode of said third main transistor, wherein a first control signal causes a binary ''''0'''' logic signal at said output terminal when binary ''''1'''' logic signals are applied to all of said main transistor command electrodes, and wherein a second control signal causes a binary ''''0'''' logic signal at said output terminal when a binary ''''1'''' logic signal is applied to any of said main transistor command electrodes.

Claim 5

An integrated circuit element including transistors of a field effect type fabricated according to a metal-oxide-semiconductor technique comprising: at least a first main transistor, a second main transistor and a third main transistor, wherein command terminals of said main transistors receive binary logic signals, and wherein said first main transistor has a first source/drain electrode coupled to an output terminal, a second source/drain electrode of said first main transistor is coupled to a first source/drain electrode of said second main transistor, a second source/drain electrode of said second main transistor is coupled to a first source/drain electrode of said third transistor and a second source/drain electrode is coupled to a ground terminal; and at least a first auxiliary transistor and a second auxiliary transistor, wherein command electrodes of said auxiliary transistors receive control signals, wherein a first source/drain electrode of said first auxiliary transistor is coupled to said ground terminal and a second source/drain electrode is coupled to said second source/drain electrode of said first main transistor, and wherein a first source/drain electrode of said second auxiliary transistor is coupled to said output terminal while said second source/drain electrode of said second auxiliary transistor is coupled to said first source/drain electrode of said third main transistor, wherein a first control signal causes a binary ''''0'''' logic signal at said output terminal when binary ''''1'''' logic signals are applied to all of said main transistor command electrodes, and wherein a second control signal causes a binary ''''0'''' logic signal at said output terminal when a binary ''''1'''' logic signal is applied to any of said main transistor command electrodes.

Claim 6

An integrated circuit of claim 3 further comprising: a reactance coupled between said output terminal and a power supply for limiting current.

Claim 7

An integrated circuit of claim 4 wherein said reactance is comprised of a transistor.

Claim 8

An integrated circuit element including transistors of a field effect type fabricated according to a metal-oxide-semiconductor technique comprising: at least one first auxiliary transistor for receiving control signals at command electrodes, wherein said first auxiliary transistor is coupled to an output terminal; at least one second auxiliary transistor for receiving said control signals at a command electrode, wherein said second auxiliary transistor is coupled to a ground terminal; and a plurality of main transistors for receiving binary logic signals at command electrodes, wherein each main transistor has a first and a second source/drain electrode, a first electrode of a first main transistor being coupled to said output terminal, and a second terminal of a last main transistor being coupled to said ground terminal, each first auxiliary transistor being coupled to two first electrodes of said main transistors, each second auxiliary transistor being coupled to two second electrodes of said main transistors, wherein a first control signal causes said output terminal to be a binary ''''0'''' signal when all of said binary logic signals are binary ''''1'''' signals, and wherein a second control signal causes said output terminal to be a binary ''''0'''' signal when any of said binary logic signals are binary ''''1'''' signals.

Claim 9

An integrated circuit element including transistors of a field effect type fabricated according to a metal-oxide-semiconductor technique comprising: at least one first auxiliary transistor for receiving control signals at command electrodes, wherein said first auxiliary transistor is coupled to an output terminal; at least one second auxiliary transistor for receiving said control signals at a command electrode, wherein said second auxiliary transistor is coupled to a ground terminal; and a plurality of main transistors for receiving binary logic signals at command electrodes, wherein each main transistor has a first and a second source/drain electrode, a first electrode of a first main transistor being coupled to said output terminal, and a second terminal of a last main transistor being coupled to said ground terminal, each first auxiliary transistor being coupled to two first electrodes of said main transistors, each second auxiliary transistor being coupled to two second electrodes of said main transistors, wherein a first control signal causes said output terminal to be a binary ''''0'''' signal when all of said binary logic signals are binary ''''1'''' signals, and wherein a second control signal causes said output terminal to be a binary ''''0'''' signal when any of said binary logic signals are binary ''''1'''' signals.

Claim 10

The integrated circuit of claim 6 further comprising a reactance for limiting current, coupled to said output terminal and adapted to be coupled to a power supply.

Claim 11

The integrated circuit of claim 7 wherein said reactance is a transistor.