US3689915A
Expired / Lapsed
US
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Encoding system
Assignee: Xerox Corp
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Filing: 1967-01-09
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Granted: 1972-09-05
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Expires: 1987-01-09
Abstract
Abstract An encoding circuit for retrieval apparatus wherein retrieval or access phrases are entered via an alphanumeric keyboard which converts each character into a m bit binary code. The phrases are then broken into segments of n characters each of which are logically compared with each other in a particular manner so that the first bit of the first segment''s first character is compared with the first bit of the second segment''s first character, etc. The results of this first comparison is then similarly compared with the character bits of the next segment, and the cycle is repeated for any additional segments.
Inventors
- 👤 Robert D De Clerck
- 👤 Glenn D Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:52
CPC Classifications
H; H03; H03M; H03M7/00; H03M7/30
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
331 words
An encoding system comprising: a. an alphanumeric-to-m binary bit converter having converter output terminals; b. a selectively actuatable source of clock pulses having an actuating input terminal and a clock output terminal; c. clock control circuit generating an actuating signal and a strobe pulse in response to a signal at said converter output terminals; d. an input shift register having at least m number of input stages, a serial output terminal, and a shift input terminal, each of said input stages having a strobe input terminal and a binary input terminal; e. first coupling means for coupling each of said converter output terminals individually to a binary input terminal of a respective input stage; f. second coupling means for coupling said strobe pulse to said strobe input terminals and for coupling said clock output terminal to said shift input terminal; g. third coupling means for coupling said actuating signal to said actuating input terminal; h. a storage shift register having a least m X n number of storage stages, a serial output terminal, a serial input terminal, and a shift input terminal, said shift input terminal being coupled to said clock output terminal; i. transfer circuit means normally enabled and adapted to be disabled for coupling said serial output terminal of said input shift register to said serial input terminal of said storage shift register only when said transfer circuit means is enabled; j. logic circuit means normally disabled and adapted to be enabled and having a comparison output terminal coupled to said serial input terminal of said storage shift register for making a logic comparison of the binary outputs at said serial output terminals of said input and storage shift registers only when said logic circuit means is enabled; and, k. decision circuit means responsive to the arrival of m X n number of said clock pulses at the shift input terminal of said storage shift register for disabling said transfer circuit means and enabling said logic comparison circuit means.
Claim 2
Dependent Claim
331 words
An encoding system comprising: a. an alphanumeric-to-m binary bit converter having converter output terminals; b. a selectively actuatable source of clock pulses having an actuating input terminal and a clock output terminal; c. clock control circuit generating an actuating signal and a strobe pulse in response to a signal at said converter output terminals; d. an input shift register having at least m number of input stages, a serial output terminal, and a shift input terminal, each of said input stages having a strobe input terminal and a binary input terminal; e. first coupling means for coupling each of said converter output terminals individually to a binary input terminal of a respective input stage; f. second coupling means for coupling said strobe pulse to said strobe input terminals and for coupling said clock output terminal to said shift input terminal; g. third coupling means for coupling said actuating signal to said actuating input terminal; h. a storage shift register having a least m X n number of storage stages, a serial output terminal, a serial input terminal, and a shift input terminal, said shift input terminal being coupled to said clock output terminal; i. transfer circuit means normally enabled and adapted to be disabled for coupling said serial output terminal of said input shift register to said serial input terminal of said storage shift register only when said transfer circuit means is enabled; j. logic circuit means normally disabled and adapted to be enabled and having a comparison output terminal coupled to said serial input terminal of said storage shift register for making a logic comparison of the binary outputs at said serial output terminals of said input and storage shift registers only when said logic circuit means is enabled; and, k. decision circuit means responsive to the arrival of m X n number of said clock pulses at the shift input terminal of said storage shift register for disabling said transfer circuit means and enabling said logic comparison circuit means.
Claim 3
Dependent Claim
70 words
An encoding system defined in claim 1 wherein said logic comparison circuit includes binary comparison means for effecting the following Boolean expression: Z A.B + A.B where A is the signal at said serial output terminal of said input shift register, B is the signal at said serial output terminal of said storage shift register, and Z is the result of said logic comparison delivered to said comparison output terminal.
Claim 4
Dependent Claim
55 words
An encoding system as defined in claim 2 further including: a. deactuating circuit means responsive to m number of said clock pulses at said shift input terminal of said input shift register for generating a deactuating signal; and, b. fourth coupling means for coupling said deactuating signal to said actuating input terminal of said source.
Claim 5
Dependent Claim
30 words
An encoding system as described in claim 1 wherein said alphanumeric-to-m binary bit converter includes a keyboard apparatus having alphanumeric keys each of which are accorded a m-bit binary code.
Claim 6
Dependent Claim
30 words
An encoding system as defined in claim 3 wherein said alphanumeric-to-m binary bit converter includes an alphanumeric keyboard, the keys of which are each accorded a m bit binary code.
Claim 7
Dependent Claim
23 words
An encoding system as defined in claim 5 wherein more than one of said keys are accorded the same m bit binary code.
Claim 8
Dependent Claim
245 words
A circuit for generating a unique group of m X n number of electrical signals which represent a specific sequence of q number of groups of m number of binary bits, said circuit comprising: a. a data input terminal adapted for receiving binary information; b. storage means having at least m X n number of stages for storing in the sequence received at said data input terminal the first m X n number of binary bits of the total q X m number of binary bits; c. logic comparison means having first and second input terminals for generating output comparison signals representative of a logic comparison of binary bits at said first and second input terminals; d. transfer circuit means coupled to said data input terminal and responsive to the storage of said first m X n number of binary bits in said storage means for translating the remaining binary bits of said total q X m number of binary bits to said first input terminal of said logic comparison means in the sequence received at said data input terminal; e. coupling means coupled between said storage means and said second input terminal for translating the binary bits stored in said m X n stages in the sequence stored to said second input terminal; and, f. translation circuit means coupled between said logic comparison means and said storage means for translating said output comparison signals in the sequence generated to said m X n stages.
Claim 9
Dependent Claim
245 words
A circuit for generating a unique group of m X n number of electrical signals which represent a specific sequence of q number of groups of m number of binary bits, said circuit comprising: a. a data input terminal adapted for receiving binary information; b. storage means having at least m X n number of stages for storing in the sequence received at said data input terminal the first m X n number of binary bits of the total q X m number of binary bits; c. logic comparison means having first and second input terminals for generating output comparison signals representative of a logic comparison of binary bits at said first and second input terminals; d. transfer circuit means coupled to said data input terminal and responsive to the storage of said first m X n number of binary bits in said storage means for translating the remaining binary bits of said total q X m number of binary bits to said first input terminal of said logic comparison means in the sequence received at said data input terminal; e. coupling means coupled between said storage means and said second input terminal for translating the binary bits stored in said m X n stages in the sequence stored to said second input terminal; and, f. translation circuit means coupled between said logic comparison means and said storage means for translating said output comparison signals in the sequence generated to said m X n stages.
Claim 10
Dependent Claim
44 words
A circuit as defined in claim 7 including clock generator means coupled to said input terminal, said storage means, and said coupling means for providing coincidence between the binary bits translated from said storage means and said input terminal to said logic comparison means.
Claim 11
Dependent Claim
50 words
A circuit as defined in claim 7 wherein said logic comparison means implements the following Boolean expression: Z A.B + A.B where Z is the said output comparison signal, A is the binary bit at said first input terminal, and B is the binary bit at said second input terminal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-05 | 1976-03-06 | 1976-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-05 | 1980-03-06 | 1980-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-05 | 1984-03-06 | 1984-09-05 | $7700.00 | Window Closed / Lapsed |