Charge storage flip-flop

Claim 2

Semiconductor storage apparatus comprising a plurality of bistable semiconductor storage cells; means forming a plurality of conduction paths for connecting the cells to circuitry adapted for selectively controlling and sensing the state of each cell; a source of electric power including means for alternately presenting a voltage of a first level and a voltage of a second and different level to the cells; each storage cell comprising: a pair of junction transistors each having emitter, base, and collector electrodes; means connecting the collector electrode of each transistor to a first terminal, said first terminal being connected to the source of electric power; means connecting the emitter electrode of each transistor to separate ones of said conduction paths; and a separate nonlinear impedance means connected into the base path of each transistor, each nonlinear impedance means including means for presenting a relatively high impedance in the base path in response to the power source voltage of the first level and for presenting a relatively low impedance in the base path in response to the power source voltage of the second level so that the state of the cell is maintained by a power source of varying voltage level.

Claim 3

Apparatus as recited in claim 1 wherein the first voltage level is in such relation to other voltage levels in the apparatus that no power is supplied to the cell while the source is at the first level and wherein the second voltage level is different from the first level and is in such relation to said other voltage levels that power is supplied to the cell while the source is at the second level.

Claim 4

Apparatus as in claim 2 wherein the transistors are phototransistors.

Claim 5

Apparatus as in claim 3 in combination with means for illuminating one of the transistors of each pair for a time sufficient to set the state of the storage cell.

Claim 6

Apparatus as recited in claim 2 wherein the nonlinear impedance means comprise a separate diode connected between the collector electrode of each transistor and the base electrode of the other transistor.

Claim 7

Apparatus as recited in claim 5 wherein the transistors are of the NPN type and the collector electrode of each transistor is connected to the anode of a said separate diode, the cathode of which diode is connected to the base electrode of the other transistor.

Claim 8

Apparatus as recited in claim 5 additionally comprising: a pair of diodes connecting the base electrode of each transistor to a second common terminal; control potential means connected to said second terminal and including means for supplying third and fourth voltage levels to said second terminal, the third level being sufficient to turn on the pair of diodes so that the base of each transistor is connected to a low impedance for discharging the transistors and the fourth level being sufficient to turn off the pair of diodes so that a relatively very high impedance is presented by the pair of diodes to the bases of the transistors.

Claim 9

Apparatus as recited in claim 7 further characterized in that the power source means and the control potential means are synchronized such that the fourth voltage level is supplied by the control potential means while the first voltage level is maintained by the power source means.

Claim 10

A semiconductor flip-flop comprising a pair of junction transistors each having emitter, base, and collector electrodes, Characterized in that each transistor includes a nonlinear impedance means for presenting a relatively low impedance to the base of each transistor when power is supplied to the flip-flop and for presenting a relatively very high impedance to the base of each transistor for ensuring a relatively slow discharge of charge stored in the emitter-base capacitance and the collector-base capacitance of one of the transistors after the power supply voltage is removed; and that the flip-flop is in combination with means for discontinuously, but recurrently, applying power to the flip-flop.

Claim 11

A semiconductor flip-flop comprising a pair of junction transistors each having emitter, base, and collector electrodes, Characterized in that each transistor includes a nonlinear impedance means for presenting a relatively low impedance to the base of each transistor when power is supplied to the flip-flop and for presenting a relatively very high impedance to the base of each transistor for ensuring a relatively slow discharge of charge stored in the emitter-base capacitance and the collector-base capacitance of one of the transistors after the power supply voltage is removed; and that the flip-flop is in combination with means for discontinuously, but recurrently, applying power to the flip-flop.

Claim 12

A flip-flop as recited in claim 9 wherein the nonlinear impedance means comprise separate diodes connected between the collector of each transistor and the base of the other transistor.

Claim 13

In an optical memory of the type having a light beam, an optical deflector, and a storage plane comprising an array of holograms in which information is stored and wherein the information stored in each particular hologram is read out by deflecting the light beam to illuminate that particular hologram so that there is produced on a readout plane a real image containing a pattern of light spots and dark spots, improved photodetection means for detecting the pattern and for translating the pattern into electrical signals corresponding to the information stored in the holograms, the improved photodetection means comprising: an array of bistable semiconductor memory cells, said cells positioned in the readout plane of the optical memory; means forming a plurality of conduction paths for connecting the cells to circuitry adapted for selectively sensing the state of each cell; each of said cells comprising: a pair of photosensitive transistors each having emitter, base, and collector electrodes; means connecting the collector electrodes of each transistor to a first common terminal adapted for connection to a source of electric power; means connecting the emitter electrode of each transistor to separate ones of said conduction paths; a first pair of nonlinear impedance means connecting the collector electrode of each transistor to the base electrode of the other transistor; and a second pair of nonlinear impedance means connecting the base electrode of each transistor to a common terminal adapted for connection to a control potential, said control potential having at least a hold level and an erase level different from the hold level; said pairs of nonlinear impedance means and said control potential levels being in relation such that when the control potential is at the erase level, the base of each transistor is connected to a low impedance through which the transistors are discharged; and when the control potential is at the hold level, said second pair of nonlinear impedance means present a relatively very high impedance to the base of each transistor and said first pair of nonlinear impedance means present a relatively low impedance to the base of each transistor when the power supply voltage is applied to the first common terminal and a relatively very high impedance to the base of each transistor when the power supply voltage is removed from the cell so that the state of the cell is maintainable by a discontinuous but recurrent power source.

Claim 14

In an optical memory of the type having a light beam, an optical deflector, and a storage plane comprising an array of holograms in which information is stored and wherein the information stored in each particular hologram is read out by deflecting the light beam to illuminate that particular hologram so that there is produced on a readout plane a real image containing a pattern of light spots and dark spots, improved photodetection means for detecting the pattern and for translating the pattern into electrical signals corresponding to the information stored in the holograms, the improved photodetection means comprising: an array of bistable semiconductor memory cells, said cells positioned in the readout plane of the optical memory; means forming a plurality of conduction paths for connecting the cells to circuitry adapted for selectively sensing the state of each cell; each of said cells comprising: a pair of photosensitive transistors each having emitter, base, and collector electrodes; means connecting the collector electrodes of each transistor to a first common terminal adapted for connection to a source of electric power; means connecting the emitter electrode of each transistor to separate ones of said conduction paths; a first pair of nonlinear impedance means connecting the collector electrode of each transistor to the base electrode of the other transistor; and a second pair of nonlinear impedance means connecting the base electrode of each transistor to a common terminal adapted for connection to a control potential, said control potential having at least a hold level and an erase level different from the hold level; said pairs of nonlinear impedance means and said control potential levels being in relation such that when the control potential is at the erase level, the base of each transistor is connected to a low impedance through which the transistors are discharged; and when the control potential is at the hold level, said second pair of nonlinear impedance means present a relatively very high impedance to the base of each transistor and said first pair of nonlinear impedance means present a relatively low impedance to the base of each transistor when the power supply voltage is applied to the first common terminal and a relatively very high impedance to the base of each transistor when the power supply voltage is removed from the cell so that the state of the cell is maintainable by a discontinuous but recurrent power source.

Claim 15

Apparatus as recited in claim 11 wherein the first pair of nonlinear impedance means comprises a separate diode connected between the collector of each transistor and the base of the other transistor, and the second pair of nonlinear means comprise a separate diode connected between the base electrode of each transistor and the second common terminal.

Claim 16

Apparatus as recited in claim 12 wherein the transistors are of the NPN type, the diodes of the first pair are disposed such that the collector of each transistor is connected to the anode of a said separate diode, the cathode of which diode is connected to the base electrode of the other transistor, and the diodes of the Second pair are disposed such that the base electrode of each transistor is connected to the anode of a said separate diode, the cathode of which diode is connected to said second common terminal.

Claim 17

Apparatus as recited in claim 11 wherein both pairs of nonlinear impedance means comprise transistors.