Gated diode memory

Claim 2

A random access memory for MOS-type circuitry, comprising: a. selectively addressable bit line means; b. selectively addressable word line means; c. selectively addressable refresh line means; d. a source of clock pulses; e. memory cell means including first diode means and gated diode means connected in opposition to one another between said bit line means and said word line means, and IGFET means having a gate electrode connected to said refresh line means and having its source-drain circuit connected between said bit line means and the gate electrode of said gated diode means; and f. second diode means connected between said clock pulse source and said bit line means for precharging said bit line means.

Claim 3

The memory array of claim 1, in which a reading operation is carried out by grounding said clock pulse source so as to discharge said bit line means through said second diode means, then re-energizing said clock pulse source and a selected word line means, and finally determining the charge level of a selected bit line means resulting from the energization of said word line means in the light of the bidirectional conductivity status of the gated diode means connected between said selected word line means and said selected bit line means.

Claim 4

The memory array of claim 2, in which means are provided to selectively energize said refresh line means following a reading operation so as to impart to said gate electrode of said gated diode means the potential of said bit line means.

Claim 5

The memory array of claim 3, in which writing is performed by impressing upon a selected bit line means a potential consistent with the information to be written, generally concurrently with the energization of a selected refresh line means.

Claim 6

A memory cell array for MOS-type circuitry, comprising, on a silicon substrate: a. first parallel diffusions forming bit line means; b. second parallel diffusions forming gated diode cathode means and being positioned between said first parallel diffusions; c. first parallel metallic strips disposed at right angles to said parallel diffusions and forming word line means; said first metallic strips forming gated diode anode means and being connected to said second diffusions by diode contact connections; d. second parallel metallic strips positioned between said first metallic strips and forming refresh line means; e. third and fourth diffusions extending generally parallel to said first and second diffusions on each side of said second metallic strip so as to form IGFETs whose gate electrodes are said second metallic strips, said third diffusions being integral with said first diffusions; f. third metallic strips extending parallel to said first and second metallic strips and having ohmic contact connections to said third diffusions and diode contact connections to said second diffusions; and g. fourth metallic strips extending generally parallel to said first and second metallic strips and having ohmic contact connections at one of their ends to said fourth diffusion, the other of their ends forming gated diode gate electrodes overlying said diode contact connections between said first metallic strips and said second diffusions.

Claim 7

A memory cell array for MOS-type circuitry, comprising, on a silicon substrate: a. first parallel diffusions forming bit line means; b. second parallel diffusions forming gated diode cathode means and being positioned between said first parallel diffusions; c. first parallel metallic strips disposed at right angles to said parallel diffusions and forming word line means; said first metallic strips forming gated diode anode means and being connected to said second diffusions by diode contact connections; d. second parallel metallic strips positioned between said first metallic strips and forming refresh line means; e. third and fourth diffusions extending generally parallel to said first and second diffusions on each side of said second metallic strip so as to form IGFETs whose gate electrodes are said second metallic strips, said third diffusions being integral with said first diffusions; f. third metallic strips extending parallel to said first and second metallic strips and having ohmic contact connections to said third diffusions and diode contact connections to said second diffusions; and g. fourth metallic strips extending generally parallel to said first and second metallic strips and having ohmic contact connections at one of their ends to said fourth diffusion, the other of their ends forming gated diode gate electrodes overlying said diode contact connections between said first metallic strips and said second diffusions.