Logic circuit for providing a short signal transit time as an integrated element

Claim 1

A circuit arrangement in emitter-coupled logic technology for the formation of a signal in a full adder with short transit time comprising: a first partial logic circuit having two emitter-coupled series connected current switches comprising first, second, third and fourth transistors with the emitters of the first and second transistors connected together and to the collector of said third transistor and the emitters of the third and fourth transistors connected together and the collectors of said second and fourth transistors connected together; a second partial logic circuit having two emitter-coupled current switches comprising, fifth, sixth, seventh and eighth transistors and the emitters of the fifth and sixth transistors connected together and to the collector of said seventh transistor and the emitters of the seventh and eighth transistors connected together, a ninth transistor connected in parallel with the fifth transistor, the bases of said second and sixth transistors connected together; 10th and 11th transistors coupled together as emitter followers, the base of the 10th transistor connected to the collectors of the second and fourth transistors, the base of the 11th transistor connected to the collectors of the sixth and eighth transistors; a joint gate resistance means with one side connected to the emitters of said 10th and 11th transistor and an output circuit terminal connected to said one side of said joint gate resistance means; a constant current source including 12th and 13th transistors with the collector of the 12th transistor connected to the emitters of the third and fourth transistors, the collector of the 13th transistor connected to the emitters of the seventh and eighth transistors, the bases of said 12th and 13th transistors connected together; a 14th transistor with its emitter connected to the base of the third transistor and its collector connected to the base of said ninth transistor; a first input terminal connected to the collector of the 14th transistor and to the base of the ninth transistor; a fifteenth transistor with its emitter connected to the base of the seventh transistor; a second input terminal connected to the collector of said 15th transistor; a third input terminal connected to the base of the first transistor and to the base of said fifth transistor; a first resistor connected between the collector and base of said 14th transistor; a second resistor connected between the base and emitter of said 14th transistor; a third resistor connected between the collector and base of said 15th transistor; a fourth resistor connected between the base and emitter of said 15th transistor; a negative supply voltage; a fifth resistor connected between said negative supply voltage and the base of said third resistor; a sixth resistor connected between the emitter of said 12th transistor and said negative supply voltage; a seventh resistor connected between the base of said seventh transistor and said negative supply voltage; an eighth resistor connected between the emitter of said 13th transistor and said negative supply voltage; the bases of said fourth and eighth transistors connected together; a ninth resistor connected between the collectors of said first and second transistors; a 10th resistor connected between the collectors of said first and sixth transistors; and the collectors of said first, said fifth, said 10th and said 11th transistors connected together.