Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
124 words
A slope limiter comprising in combination: a signal input circuit; first circuit means including a first signal delay circuit and a subtraction circuit connected to said signal input circuit and adapted to provide a difference signal representing the difference in amplitude between first and second input signals; second circuit means connected to said first circuit means for receipt of said difference signal and including division circuit means adapted to provide a signal which is a fractional part of said difference signal; and third circuit means connected to said input circuit and to said second circuit means and including means for adding the output signal of said division circuit means to said first input signal, and subtracting said output signal from said second input signal.
Claim 2
Dependent Claim
124 words
A slope limiter comprising in combination: a signal input circuit; first circuit means including a first signal delay circuit and a subtraction circuit connected to said signal input circuit and adapted to provide a difference signal representing the difference in amplitude between first and second input signals; second circuit means connected to said first circuit means for receipt of said difference signal and including division circuit means adapted to provide a signal which is a fractional part of said difference signal; and third circuit means connected to said input circuit and to said second circuit means and including means for adding the output signal of said division circuit means to said first input signal, and subtracting said output signal from said second input signal.
Claim 3
Dependent Claim
41 words
The apparatus of claim 1 wherein said third circuit means includes a second delay circuit connected between an addition circuit and a second subtraction circuit, said addition circuit and said second subtraction circuit each being connected to said division circuit means.
Claim 4
Dependent Claim
47 words
The apparatus of claim 1 and including fourth circuit means connected to said third and second circuit means, said fourth circuit means including means to inhibit output signals from said division circuit means to said third circuit means unless said difference signal is of a predetermined magnitude.
Claim 5
Dependent Claim
44 words
The apparatus of claim 3 wherein said fourth circuit means includes a reference signal generator and a comparator connected to receive said difference signal and compare it to a reference signal, and a gate circuit connected to said division circuit and to said comparator.
Claim 6
Dependent Claim
126 words
A slope limiter comprising in combination: first signal storage circuit means, first subtraction circuit means, and division circuit means connected in series circuit and operatiVe to provide a first signal which is a fraction of the difference between a first input signal applied to and stored in said storage circuit means and a second input signal applied directly to said subtraction circuit means; addition circuit means and second subtraction circuit means each connected to said division circuit means; second signal storage circuit means connected between said addition circuit means and said second subtraction circuit means; signal output circuit means connected to said addition circuit means; and signal input circuit means connected to said first signal storage circuit means and to each of said subtraction circuit means.
Claim 7
Dependent Claim
126 words
A slope limiter comprising in combination: first signal storage circuit means, first subtraction circuit means, and division circuit means connected in series circuit and operatiVe to provide a first signal which is a fraction of the difference between a first input signal applied to and stored in said storage circuit means and a second input signal applied directly to said subtraction circuit means; addition circuit means and second subtraction circuit means each connected to said division circuit means; second signal storage circuit means connected between said addition circuit means and said second subtraction circuit means; signal output circuit means connected to said addition circuit means; and signal input circuit means connected to said first signal storage circuit means and to each of said subtraction circuit means.
Claim 8
Dependent Claim
35 words
Apparatus as defined in claim 5 and including threshold circuit means connected to said first subtraction circuit means, and signal gating circuit means connected to said division circuit means and to said threshold circuit means.
Claim 9
Dependent Claim
32 words
Apparatus as defined in claim 5 wherein each of said signal storage circuit means are digital signal buffer units each adapted to receive and store at least one parallel bit binary word.
Claim 10
Dependent Claim
47 words
The apparatus of claim 5 wherein each of said signal storage means comprises a plurality of binary signal buffer units connected in series circuit with each buffer unit adapted to store a parallel bit binary word, and means for applying clock pulse signals to the buffer units.
Claim 11
Dependent Claim
109 words
A slope limiter as defined in claim 5 and further including: third signal storage circuit means, third subtraction circuit means, and second division circuit means connected in series circuit with said output circuit means being connected to said third storage circuit means and to said third subtraction circuit means; second addition circuit means and fourth subtraction circuit means each connected to said second division circuit means; means connecting said fourth subtraction circuit means to said output circuit means; fourth signal storage circuit means connected between said second addition circuit means and said fourth subtraction circuit means; and a second signal output circuit connected to said second addition circuit means.
Claim 12
Dependent Claim
61 words
A system as defined in claim 9 wherein said first and second signal storage means comprise digital buffer units each adapted to store in serial sequence the same number of parallel bit binary words, and said third and fourth signal storage means comprise digital buffer units each adapted to store in serial sequence the same number of parallel bit binary words.
Claim 13
Dependent Claim
15 words
The system of claim 10 wherein said first and second division circuits have different divisors.
Claim 14
Dependent Claim
29 words
The system of claim 11 wherein the number of words stored in said first buffer unit is different from the number of words stored in said third buffer unit.
Claim 15
Dependent Claim
97 words
A slope limiter comprising in combination: a signal input circuit; first circuit means connected to said input circuit and including a first signal delay circuit, a subtraction circuit, and a division circuit operatively interconnected to provide a difference signal representing a fraction of the difference in amplitude between first and second input signals; and second circuit means connected to said input circuit and to said first circuit means and including means for adding an output signal from said first circuit means to said first input signal, and for subtracting said output signal from said second input signal.
Claim 16
Dependent Claim
97 words
A slope limiter comprising in combination: a signal input circuit; first circuit means connected to said input circuit and including a first signal delay circuit, a subtraction circuit, and a division circuit operatively interconnected to provide a difference signal representing a fraction of the difference in amplitude between first and second input signals; and second circuit means connected to said input circuit and to said first circuit means and including means for adding an output signal from said first circuit means to said first input signal, and for subtracting said output signal from said second input signal.
Claim 17
Dependent Claim
33 words
The apparatus of claim 13 wherein said second circuit means includes an addition circuit, a second subtraction circuit, and a second delay circuit connected between said addition circuit and said second subtraction circuit.