Automatic gain control rf-if amplifier

Claim 2

A differential amplifier circuit including, in combination: a first differential amplifier stage including: a first pair of transistors, each having control, first, and second electrodes, with the second electrodes being coupled to a first common point, first load impedance means coupling the first electrode of one transistor of the first pair to a source of operating potential, the first electrode of the other transistor of the first pair being coupled directly to said source of operating potential; a first input transistor, having control, first and second electrodes, the first electrode of which is connected to said first common point, a second pair of transistors each having control, first, and second electrodes, with the second electrodes being coupled to a second common point, second load impedance means coupling the first electrode of one transistor of the second pair to said source of operating potential, the first electrode of the other transistor of the second pair being coupled directly to said source of operating potential; a second input transistor, having control, first and second electrodes, the first electrode of which is connected to said second common point and the second electrode of which is further connected to the second electrode of said first input transistor, the control electrodes of said first and second input transistors being differentially coupled to input terminals for receiving thereat a differential input signal. means for supplying a gain control voltage, the control electrodes of the one of the transistors of each of said first and second pairs of differentially coupled transistors being connected at a first common node, the control electrodes of the other of the transistors of each of said pairs of differentially coupled transistors being connected at a second common node for receiving at said common nodes said gain control voltage, said common nodes being a virtual ground and eliminating the need for RF bypass capacitors for said first and second pairs of transistors; and the output of said circuit being obtained across the first electrodes of the one of the transistors of the first and second pairs of transistors.

Claim 3

The differential amplifier circuit defined in claim 1 which further includes a second differential amplifier stage having at least first and second differentially coupled transistors therein which are coupled respectively to the first electrodes of the one transistor in each of said first and second transistor pairs, so that a common mode signal coupled to said first and second transistor pairs is rejected in said second stage because the differential conductivity in said second stage is unchanged by a common mode signal applied thereto.

Claim 4

The differential amplifier circuit defined in claim 2 wherein said second stage further includes third and fourth transistors cascaded to said first and second transistors in said second stage to form therewith a pair of Darlington connections, said third and fourth transistors interconnecting said first and second transistors in said second stage with the outputs of transistors in said first and second pairs of transistors in said first stage, said third and fourth transistors having a high input impedance for buffering the inputs to said first and second differentially cOnnected transistors in said second stage and enhancing the frequency response of the amplifier circuit.

Claim 5

The differential amplifier circuit defined in claim 3 which further includes: a first bias network connected to said first differential amplifier stage for setting the DC bias levels for said first and second transistor pairs and said first and second input transistors, a second bias stage connected to said second differential amplifier stage for establishing the bias levels thereat, and a current sink connected to said second differential amplifier stage for establishing a constant current therethrough.

Claim 6

A differential amplifier circuit adapted to be fabricated in monolithic integrated form and including, in combination: a first differential amplifier stage having a first pair of transistors each having control, first and second electrodes, with the second electrodes being differentially coupled therein at a first common point, a second pair of transistors each having control, first and second electrodes, with the second electrodes being differentially coupled to a second common point, one transistor in each of said first and second pairs of transistors having a load resistor connected thereto, a first input transistor having control, first and second electrodes, with the first electrode being coupled to said first common point, a second input transistor having control, first and second electrodes, with the first electrode being coupled to said second common point with the second electrode thereof being further differentially coupled to the second electrode of said first input transistor, said first and second input transistors operative to receive differential signals at the control electrodes thereof and to differentially control the current flowing in said first and second pairs of transistors in said first differential amplifier stage, the control electrodes of the other transistor in each of said first and second pairs of transistors being connected to a common node to which an automatic gain control voltage is applied for controlling the DC level of current flow in said first and second load resistors, said common node having a virtual ground and thereby requiring no by-pass capacitors at said first and second pairs of differentially coupled transistors for said first stage to operate in a common base mode; a second, output differential amplifier stage having at least first and second differentially coupled transistors therein from which an output signal may be derived, said first and second transistors in said output stage being differentially coupled to said first and second load resistors in said input stage whereby a common mode signal in said input stage does not affect the conductivity of said first and second transistors in said output stage; and third and fourth transistors cascaded to said first and second transistors, respectively, in said output stage and further interconnecting said first and second transistors in said output stage to said first and second load resistors in said input stage, said third and fourth transistors in said output stage having a high input impedance and low output impedance and enhancing the frequency response of the amplifier circuit.

Claim 7

A differential amplifier circuit adapted to be fabricated in monolithic integrated form and including, in combination: a first differential amplifier stage having a first pair of transistors each having control, first and second electrodes, with the second electrodes being differentially coupled therein at a first common point, a second pair of transistors each having control, first and second electrodes, with the second electrodes being differentially coupled to a second common point, one transistor in each of said first and second pairs of transistors having a load resistor connected thereto, a first input transistor having control, first and second electrodes, with the first electrode being coupled to said first common point, a second input transistor having control, first and second electrodes, with the first electrode being coupled to said second common point with the second electrode thereof being further differentially coupled to the second electrode of said first input transistor, said first and second input transistors operative to receive differential signals at the control electrodes thereof and to differentially control the current flowing in said first and second pairs of transistors in said first differential amplifier stage, the control electrodes of the other transistor in each of said first and second pairs of transistors being connected to a common node to which an automatic gain control voltage is applied for controlling the DC level of current flow in said first and second load resistors, said common node having a virtual ground and thereby requiring no by-pass capacitors at said first and second pairs of differentially coupled transistors for said first stage to operate in a common base mode; a second, output differential amplifier stage having at least first and second differentially coupled transistors therein from which an output signal may be derived, said first and second transistors in said output stage being differentially coupled to said first and second load resistors in said input stage whereby a common mode signal in said input stage does not affect the conductivity of said first and second transistors in said output stage; and third and fourth transistors cascaded to said first and second transistors, respectively, in said output stage and further interconnecting said first and second transistors in said output stage to said first and second load resistors in said input stage, said third and fourth transistors in said output stage having a high input impedance and low output impedance and enhancing the frequency response of the amplifier circuit.

Claim 8

The differential amplifier circuit as defined in claim 1 which further includes a first bias network connected between a voltage supply terminal and a point of reference potential having series resistors therein for establishing desired DC biasing levels at said first, input differential amplifier stage, said first bias network further having diodes connected in series with said resistors for providing temperature compensation at said input differential amplifier stage, said first bias network including cascaded transistors therein connected between said resistors and said load resistors in said input differential amplifier stage for preventing the collectors of said one transistor in each of said first and second paIrs of transistors from rising to the supply voltage of said amplifier circuit, said first bias network further including another transistor connected between said cascaded transistors and said one transistor in each of said pairs of transistors for establishing the bias potential thereat, and a further transistor connected between said another transistor and said first and second input transistors for establishing the DC bias levels thereat.

Claim 9

The differential amplifier circuit defined in claim 6 which further includes a second bias network having resistors connected in series with temperature compensating diodes between a voltage supply terminal and a point of reference potential, and a current source connected between said first, second, third and fourth transistors in said output differential amplifier stage and a point of reference potential and further connected to a bias point in said second bias network, said current source providing a constant current through said output differential amplifier stage.

Claim 10

The differential amplifier circuit defined in claim 7 wherein said one transistor in each of said first and second pairs of transistors being connected to a common point, and a resistor connected between said last named common point and said common node to which the other transistor in each of said transistor pairs is connected.