Division utilizing multiples of the divisor stored in an addressable memory

Claim 2

In a computer, a method of dividing numbers expressed in a predetermined base or radix comprising the steps of: a. storing the dividend as a set of integers in a dividend register, b. addressably storing a plurality of successive multiples of the divisor in a plurality of registers, said plurality equal to the base or radix raised to a predetermined integral power, c. comparing a subset of the integers of the dividend with each multiple of the divisor in a comparator to thereby determine the largest said multiple equal to or less than said subset, d. subtracting the largest said multiple from said subset in a subtractor and adjoining futher dividend integers to the difference thereby to form a further subset of integers, e. storing the address of the largest said multiple to form a quotient, f. repeating steps c to e, but utilizing said further subset of integers as the subset of integers of the dividend until all dividend integers have been utilized.

Claim 3

Method as in claim 1 wherein each address corresponds to the multiplier of the divisor multiple stored thereat.

Claim 4

Method as in claim 1 wherein the base or radix is two and the predetermined integral power is three.

Claim 5

In a computer, a method of performing division on binary numbers comprising the steps of: a. stOring the dividend as a set of binary digits in a dividend register, b. addressably storing a plurality of successive multiples of the divisor in a plurality of registers, said plurality equal to two raised to a predetermined integral power, c. establishing a first subset of the integers of the dividend in accordance with the number of divisor digits, d. comparing said subset of the integers with each multiple of the divisor thereby to determine the largest multiple equal to or less than said subset, e. subtracting said multiple from said first subset in a subtractor and appending to the difference further digits from said dividend thereby to form a further subset, f. storing the address of said multiple in a register to form a partial quotient, g. comparing said further subset with each multiple of the divisor in a comparator to thereby determine the largest multiple equal to or less than said further subset, h. subtracting the multiple determined by step (g) from said further subset in said subtractor and appending to the difference further digits from said dividend, j. storing the address of the multiple determined by step (g) to form further quotient digits, k. continuing the process as set forth in steps (g), (h) and (j) until there are no further dividend digits to be utilized.

Claim 6

In a computer, a method of performing division on binary numbers comprising the steps of: a. stOring the dividend as a set of binary digits in a dividend register, b. addressably storing a plurality of successive multiples of the divisor in a plurality of registers, said plurality equal to two raised to a predetermined integral power, c. establishing a first subset of the integers of the dividend in accordance with the number of divisor digits, d. comparing said subset of the integers with each multiple of the divisor thereby to determine the largest multiple equal to or less than said subset, e. subtracting said multiple from said first subset in a subtractor and appending to the difference further digits from said dividend thereby to form a further subset, f. storing the address of said multiple in a register to form a partial quotient, g. comparing said further subset with each multiple of the divisor in a comparator to thereby determine the largest multiple equal to or less than said further subset, h. subtracting the multiple determined by step (g) from said further subset in said subtractor and appending to the difference further digits from said dividend, j. storing the address of the multiple determined by step (g) to form further quotient digits, k. continuing the process as set forth in steps (g), (h) and (j) until there are no further dividend digits to be utilized.

Claim 7

Method as in claim 4 wherein the addresses of the divisor multiples correspond respectively to the multipliers of the divisor.

Claim 8

Method as in claim 4 wherein the predetermined integral power is three.

Claim 9

Apparatus for dividing one number by another number comprising: a. a plurality of addressable storage registers for storing successive integral multiples of the divisor, b. first storage means for successively storing predetermined subsets of digits derived entirely or partially from the dividend, c. comparing means for simultaneously comparing the contents of all of said addressable storage registers with the contents of said first storage means and providing an output indicative of a storage register whose contents are equal to the contents of said first storage means, or alternately the storage register containing the largest multiple less than the contents of said first storage means, d. subtracting means for subtracting the contents of the storage register whose contents are equal to the contents of the first storage means from the contents of said first storage means, or alternately subtracting the contents of the storage register containing the largest multiple less than the contents of said first storage means, from the contents of said first storage means, e. means for transferring the difference resulting from the subtraction to said first storage means to form a further partial subset, f. second storage means for storing the address of the storage register indicated by said comparing means as a quotient subset, g. control means for operating said apparatus until all digits from the dividend have been utilized, and h. means for detecting when all digits from the dividend have been utilized.

Claim 10

Apparatus for dividing one number by another number comprising: a. a plurality of addressable storage registers for storing successive integral multiples of the divisor, b. first storage means for successively storing predetermined subsets of digits derived entirely or partially from the dividend, c. comparing means for simultaneously comparing the contents of all of said addressable storage registers with the contents of said first storage means and providing an output indicative of a storage register whose contents are equal to the contents of said first storage means, or alternately the storage register containing the largest multiple less than the contents of said first storage means, d. subtracting means for subtracting the contents of the storage register whose contents are equal to the contents of the first storage means from the contents of said first storage means, or alternately subtracting the contents of the storage register containing the largest multiple less than the contents of said first storage means, from the contents of said first storage means, e. means for transferring the difference resulting from the subtraction to said first storage means to form a further partial subset, f. second storage means for storing the address of the storage register indicated by said comparing means as a quotient subset, g. control means for operating said apparatus until all digits from the dividend have been utilized, and h. means for detecting when all digits from the dividend have been utilized.

Claim 11

Apparatus as in claim 7 further comprising third storage means for storing the difference resulting from the subtraction whereby upon the completion of operation of the apparatus said difference constitutes the remainder.

Claim 12

Apparatus for performing binary divisions comprising a. a dividend register having a predetermined bit capacity, b. a divisor register having a predetermined bit capacity c. a minuend register and first transfer means for transferring data from said dividend register into said minuend register in the form of subsets of data of predetermined length, d. a plurality of addressable storage registers, e. second transfer means coupling said divisor register to said addressable storage registers, said second transfer means effecting multiplication of the divisor register contents by successive integral multipliers and storing each product in the storage reGister whose address corresponds to the multiplier, f. a comparator means for comparing the contents of the storage registers with the contents of the minuend register in order to determine the storage register containing a divisor multiple equal to the contents of the minuend register or alternately the storage register containing the largest divisor multiple less than the contents of the minuend register, g. a quotient register and means for transferring the address of the storage register determined by the comparator means to said quotient register, h. a subtraction means for subtracting the contents of the storage register determined by the comparator means from the contents of the minuend register, j. a difference register for storing the difference resulting from the subtraction, k. third transfer means for transferring the contents of the difference register to the minuend register and l. cycling means for providing a succession of control signals until all dividend digits have been transferred to said minuend register and the contents of the difference register are less than the contents of the divisor register.

Claim 13

Apparatus for performing binary divisions comprising a. a dividend register having a predetermined bit capacity, b. a divisor register having a predetermined bit capacity c. a minuend register and first transfer means for transferring data from said dividend register into said minuend register in the form of subsets of data of predetermined length, d. a plurality of addressable storage registers, e. second transfer means coupling said divisor register to said addressable storage registers, said second transfer means effecting multiplication of the divisor register contents by successive integral multipliers and storing each product in the storage reGister whose address corresponds to the multiplier, f. a comparator means for comparing the contents of the storage registers with the contents of the minuend register in order to determine the storage register containing a divisor multiple equal to the contents of the minuend register or alternately the storage register containing the largest divisor multiple less than the contents of the minuend register, g. a quotient register and means for transferring the address of the storage register determined by the comparator means to said quotient register, h. a subtraction means for subtracting the contents of the storage register determined by the comparator means from the contents of the minuend register, j. a difference register for storing the difference resulting from the subtraction, k. third transfer means for transferring the contents of the difference register to the minuend register and l. cycling means for providing a succession of control signals until all dividend digits have been transferred to said minuend register and the contents of the difference register are less than the contents of the divisor register.

Claim 14

Apparatus as in claim 9 wherein the bit capacity of the several registers set forth therein is integrally divisible by three.

Claim 15

Apparatus as in claim 9 wherein the number of bits in said subsets is integrally divisible by three.

Claim 16

Apparatus as in claim 9 wherein said first transfer means is coupled to said divisor register and said cycling means and controlled in accordance with the number of significant bits in said divisor register thereby to transfer data to predetermined bit positions in said minuend register.

Claim 17

Apparatus as in claim 9 wherein said second transfer means comprises a plurality of shifting means and a plurality of adding means.

Claim 18

Apparatus as in claim 9 wherein said comparator means compares simultaneously the contents of all storage registers with the contents of the minuend register.

Claim 19

Apparatus as in claim 14 wherein said comparator means generates output signals for all storage registers whose contents are equal to or less than the contents of the minuend register, and an output gate coupled to each output of the comparator means, said gate being enabled by its respective comparator means output and disabled by any output of higher rank from the comparator means so that one gate only provides an output.

Claim 20

Apparatus as in claim 15 wherein the output from said gate transfers the address of its corresponding storage register to the quotient register and the contents of its corresponding storage register to a subtrahend register.

Claim 21

Apparatus as in claim 9 wherein seven storage registers are provided having addresses 001 to 111.