Pulse height analyzer

Claim 2

A pulse height analyzer for providing an output pulse signal in response to an input signal having a maximum amplitude between predetermined lower and upper amplitude levels, the circuit comprising: a. first and second means responsive to said input signal for respectively providing first and second output control signals when said input signal amplitude exceeds said lower and upper levels, respectively; b. bistable means responsive to said first and second output control signals for providing a third output control signal normally being of a first level, changing to a second level upon receipt of both a first control signal and a second control signal, and returning to a first level upon the receipt of a succeeding first control signal; and c. gate means responsive to the receipt of a said first control signal and a said third control signal for normally developing a said output pulse signal of a first level and for developing an output pulse signal of a second level during a time interval commencing after the receipt of a said first control signal when a said third control signal is of a first level.

Claim 3

The analyzer of claim 1, wherein said gate means includes first circuit means, for after the receipt of a said first output control signal, providing a said output signal, and second circuit means responsive to said third output control signal of a second level to inhibit a said output signal.

Claim 4

The analyzer of claim 2, wherein said first and second means respectively comprise first and second signal amplitude comparator means.

Claim 5

The analyzer of claim 3, further including variable means for biasIng said first and second comparator means to determine said lower and upper levels.

Claim 6

The analyzer of claim 2, wherein said gate means comprises an OR gate.

Claim 7

The analyzer of claim 2, wherein said gate means comprises an AND gate.

Claim 8

The analyzer of claim 1, wherein said first and second means respectively comprise first and second signal amplitude comparator means.

Claim 9

The analyzer of claim 7, further including variable means for biasing said first and second comparator means to determine said lower and upper levels.

Claim 10

The analyzer of claim 1, wherein said gate means comprises an AND gate.

Claim 11

A pulse height analyzer for providing an output signal in response to an input signal, having a maximum amplitude lying between predetermined lower and upper amplitude levels, the circuit comprising: a. first and second comparator means responsive to said input signal for respectively providing first and second output control signals of a first binary level when said input signal amplitude exceeds said lower and upper levels, respectively; b. gate means for receiving two input signals, providing an output signal of a second binary level when at least one of said input signals is of said first level, and providing an output signal of said first level when both of said input signals are of said second level; c. first circuit means for applying a said first output control signal to said gate means; d. bistable means responsive to said first and second output control signals for providing a third output control signal, said third output control signal normally being of said second level when said first input control signal changes from said first level to said second level, said third output control signal being prevented from changing to said second level in response to said first output control signal changing to said second level by said second output control signal changing to said first level and then to said second level while said first output control signal is of said first level; and e. second circuit means for applying a said third output control signal to said gate means.

Claim 12

A pulse height analyzer for providing an output signal in response to an input signal, having a maximum amplitude lying between predetermined lower and upper amplitude levels, the circuit comprising: a. first and second comparator means responsive to said input signal for respectively providing first and second output control signals of a first binary level when said input signal amplitude exceeds said lower and upper levels, respectively; b. gate means for receiving two input signals, providing an output signal of a second binary level when at least one of said input signals is of said first level, and providing an output signal of said first level when both of said input signals are of said second level; c. first circuit means for applying a said first output control signal to said gate means; d. bistable means responsive to said first and second output control signals for providing a third output control signal, said third output control signal normally being of said second level when said first input control signal changes from said first level to said second level, said third output control signal being prevented from changing to said second level in response to said first output control signal changing to said second level by said second output control signal changing to said first level and then to said second level while said first output control signal is of said first level; and e. second circuit means for applying a said third output control signal to said gate means.

Claim 13

The analyzer of claim 10, wherein said gate means comprises an OR gate.

Claim 14

The analyzer of claim 10, wherein said gate means comprises an AND gate.

Claim 15

A pulse height analyzer for providing an output signal in response to an input signal having a maximum amplitude lying between predetermined lower and upper amplitude levels, the circuit comprising: a. first and second comparator means responsive to said input signal for respectively providing first and second output control signals that are high when said input signal amplitude exceeds said lower and upper levels, respectively; b. a NOR gate for receiving two input signals, providing a low output signal when at least one of said input signals is high, and providing a high output signal when both of said input signals are low; c. first circuit means for applying said first output control signal as one input signal to said NOR gate; d. an inverter for inverting said first output control signal and providing an inverted first output control signal; e. bistable means for receiving said second output control signal and said inverted first output control signal for providing a third output control signal, said third output control signal normally being at a first binary level when said inverted first output control signal changes from a first to a second binary level, said third output control signal being prevented from changing to a first binary level in response to said inverted first output control signal changing to a second binary level by said second output control signal changing from a second binary level to a first binary level while said inverted first output control signal is at a first binary level; and f. second circuit means for applying said third output control signal as a second input signal to said NOR gate.

Claim 16

A pulse height analyzer for providing an output signal in response to an input signal having a maximum amplitude lying between predetermined lower and upper amplitude levels, the circuit comprising: a. first and second comparator means responsive to said input signal for respectively providing first and second output control signals that are high when said input signal amplitude exceeds said lower and upper levels, respectively; b. a NOR gate for receiving two input signals, providing a low output signal when at least one of said input signals is high, and providing a high output signal when both of said input signals are low; c. first circuit means for applying said first output control signal as one input signal to said NOR gate; d. an inverter for inverting said first output control signal and providing an inverted first output control signal; e. bistable means for receiving said second output control signal and said inverted first output control signal for providing a third output control signal, said third output control signal normally being at a first binary level when said inverted first output control signal changes from a first to a second binary level, said third output control signal being prevented from changing to a first binary level in response to said inverted first output control signal changing to a second binary level by said second output control signal changing from a second binary level to a first binary level while said inverted first output control signal is at a first binary level; and f. second circuit means for applying said third output control signal as a second input signal to said NOR gate.

Claim 17

A pulse height analyzer for providing an output signal in response to an input signal, having a maximum amplitude lying between predetermined lower and upper amplitude levels, the circuit comprising: a. first and second comparator means responsive to said input signal for respectively providing first and second output control signals that are low when said input signal amplitude exceeds said lower and upper levels, respectively; b. a NAND gate for receiving two input signals, providing a high output signal when at least one of said input signals is low, and providing a low output signal when both of said input signals are high; c. first connecting means for providing said first output control signal as one input signal to said NAND gate; d. bistable means for receiving said first and second output control signals and providing a third output control signal, said third output control signal normally being high when said first output control signal goes from low to high, said third output control signal being prevented from going high in response to said first output control signal going high by said second output control signal going low and then high while said first output control signal is low; and e. second connecting means for providing said third output control signal as a second input signal to said NAND gate.

Claim 18

A pulse height analyzer for providing an output signal in response to an input signal, having a maximum amplitude lying between predetermined lower and upper amplitude levels, the circuit comprising: a. first and second comparator means responsive to said input signal for respectively providing first and second output control signals that are low when said input signal amplitude exceeds said lower and upper levels, respectively; b. a NAND gate for receiving two input signals, providing a high output signal when at least one of said input signals is low, and providing a low output signal when both of said input signals are high; c. first connecting means for providing said first output control signal as one input signal to said NAND gate; d. bistable means for receiving said first and second output control signals and providing a third output control signal, said third output control signal normally being high when said first output control signal goes from low to high, said third output control signal being prevented from going high in response to said first output control signal going high by said second output control signal going low and then high while said first output control signal is low; and e. second connecting means for providing said third output control signal as a second input signal to said NAND gate.